From 062a014c7c956891db1ffac0ada6c6b2aeb38bf3 Mon Sep 17 00:00:00 2001
From: Alexander Heldt <me@alexanderheldt.se>
Date: Sat, 3 Aug 2024 11:49:46 +0200
Subject: [PATCH] Add `timer.{h, c}`

---
 src/timer.c | 22 ++++++++++++++++++++++
 src/timer.h | 38 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 60 insertions(+)
 create mode 100644 src/timer.c
 create mode 100644 src/timer.h

diff --git a/src/timer.c b/src/timer.c
new file mode 100644
index 0000000..cb794d3
--- /dev/null
+++ b/src/timer.c
@@ -0,0 +1,22 @@
+#include "rcc.h"
+#include "timer.h"
+
+void tim4_init(void) {
+  // Enable timer
+  RCC->APB1ENR |= RCC_APB1ENR_TIM4_ENABLE;
+
+  // Reset timer
+  TIM4->CR1 = 0x0000;
+  TIM4->CR2 = 0x0000;
+
+  // Set prescaler
+  // f_clk = 48MHz -> /48000 = 1KHz counting frequency = 1ms
+  TIM4->PSC = (uint16_t) 48000 - 1;
+
+  // Set ARR to maximum value to get 1ms between updates
+  TIM4->ARR = (uint16_t) 0xFFFF;
+}
+
+void tim4_start(void) {
+  TIM4->CR1 |= TIM4_ENABLE;
+}
diff --git a/src/timer.h b/src/timer.h
new file mode 100644
index 0000000..18eebc4
--- /dev/null
+++ b/src/timer.h
@@ -0,0 +1,38 @@
+#ifndef TIMER_H_
+#define TIMER_H_
+
+#include <inttypes.h>
+
+struct timer {
+  volatile uint32_t CR1;    // Control register 1
+  volatile uint32_t CR2;    // Control register 2
+  volatile uint32_t SMCR;   // Slave mode control register
+  volatile uint32_t DIER;   // DMA/interrupt enable registe
+  volatile uint32_t SR;     // Status register
+  volatile uint32_t EGR;    // Event generation register
+  volatile uint32_t CCMR1;  // Capture/compare mode register 1
+  volatile uint32_t CCMR2;  // Capture/compare mode register 2
+  volatile uint32_t CCER;   // Capture/compare enable register
+  volatile uint32_t CNT;    // Counter
+  volatile uint32_t PSC;    // Prescalar
+  volatile uint32_t ARR;    // Auto-reload register
+  volatile uint32_t RCR;    // Repetition counter registe
+  volatile uint32_t CCR1;   // Capture/compare register 1
+  volatile uint32_t CCR2;   // Capture/compare register 2
+  volatile uint32_t CCR3;   // Capture/compare register 3
+  volatile uint32_t CCR4;   // Capture/compare register 4
+  volatile uint32_t BDTR;   // Break and dead-time register
+  volatile uint32_t DCR;    // DMA control register
+  volatile uint32_t DMAR;   // DMA address for full transfer
+};
+
+#define TIM4_BASE_ADDR (0x40000800U)
+#define TIM4 ((struct timer *) TIM4_BASE_ADDR)
+
+#define TIM4_CR_CEN_BIT 0
+#define TIM4_ENABLE (1 << TIM4_CR_CEN_BIT)
+
+void tim4_init(void);
+void tim4_start(void);
+
+#endif