wip

build/main.i

@@ -2097,9 +2097,17 @@ struct rcc {
 #define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT)
 
 
+
+#define RCC_AHB1ENR_GPIOAEN_BIT 0
+#define RCC_AHB1ENR_GPIOAEN_ENABLE (1 << RCC_AHB1ENR_GPIOAEN_BIT)
+
+
 #define RCC_APB1ENR_PWREN_BIT 28
 #define RCC_APB1ENR_PWREN_CLOCK_ENABLE (1 << RCC_APB1ENR_PWREN_BIT)
 
+#define RCC_APB1ENR_USART2EN_BIT 17
+#define RCC_APB1ENR_USART2EN_ENABLE (1 << RCC_APB1ENR_USART2EN_BIT)
+
 #define RCC_APB1ENR_TIM4_BIT 2
 #define RCC_APB1ENR_TIM4_ENABLE (1 << RCC_APB1ENR_TIM4_BIT)
 # 5 "src/main.c" 2
@@ -2119,10 +2127,36 @@ struct gpio {
   volatile uint32_t ODR;
   volatile uint32_t BSRR;
   volatile uint32_t LCKR;
-  volatile uint32_t AFRL[2];
-  volatile uint32_t AFRH[2];
+  volatile uint32_t AFRL;
+  volatile uint32_t AFRH;
 };
 
+#define GPIOA_BASE_ADDR (0x40020000U)
+#define GPIOA ((struct gpio *) GPIOA_BASE_ADDR)
+
+
+#define GPIO_MODER_MODER3_BIT 7
+#define GPIO_MODER_MODER3_MASK (0b11)
+#define GPIO_MODER_MODER3_AF (0b10)
+
+#define GPIO_MODER_MODER2_BIT 4
+#define GPIO_MODER_MODER2_MASK (0b11)
+#define GPIO_MODER_MODER2_AF (0b10)
+
+
+#define GPIO_AFRL_AFRL3_BIT 12
+#define GPIO_AFRL_AFRL3_MASK (0b1111)
+#define GPIO_AFRL_AFRL3_USART2_RX (0b0111)
+
+#define GPIO_AFRL_AFRL2_BIT 8
+#define GPIO_AFRL_AFRL2_MASK (0b1111)
+#define GPIO_AFRL_AFRL2_USART2_TX (0b0111)
+
+
+
+
+
+
 #define GPIO_BASE_ADDR (0x40020000U)
 #define GPIO_PORT_OFFSET (0x400U)
 #define GPIO(port) ((struct gpio*)(uintptr_t)(GPIO_BASE_ADDR + (GPIO_PORT_OFFSET * port)))
@@ -2144,9 +2178,9 @@ typedef enum {
 
 void gpio_set_mode(uint16_t pin, GPIO_MODE mode);
 void gpio_write(uint16_t pin, 
-# 40 "src/gpio.h" 3 4
+# 66 "src/gpio.h" 3 4
                              _Bool 
-# 40 "src/gpio.h"
+# 66 "src/gpio.h"
                                   val);
 # 6 "src/main.c" 2
 # 1 "src/flash.h" 1
@@ -2237,12 +2271,58 @@ struct timer {
 #define TIM4_BASE_ADDR (0x40000800U)
 #define TIM4 ((struct timer *) TIM4_BASE_ADDR)
 
-#define TIM4_CR_CEN_BIT 0
-#define TIM4_ENABLE (1 << TIM4_CR_CEN_BIT)
+#define TIM_CR1_CEN_BIT 0
+#define TIM_ENABLE (1 << TIM_CR1_CEN_BIT)
 
 void tim4_init(void);
 void tim4_start(void);
 # 9 "src/main.c" 2
+# 1 "src/usart.h" 1
+
+#define USART_H_ 
+
+
+
+struct usart {
+  volatile uint32_t SR;
+  volatile uint32_t DR;
+  volatile uint32_t BRR;
+  volatile uint32_t CR1;
+  volatile uint32_t CR2;
+  volatile uint32_t CR3;
+  volatile uint32_t GTPR;
+};
+
+#define USART2_BASE_ADDR (0x40004400U)
+#define USART2 ((struct usart *) USART2_BASE_ADDR)
+
+
+
+#define USART_CR1_OVER8_BIT 15
+#define USART_CR1_OVER8_8 (1 << USART_CR1_OVER8_BIT)
+
+
+#define USART_CR1_UE_BIT 13
+#define USART_CR1_UE_ENABLE (1 << USART_CR1_UE_BIT)
+
+
+#define USART_CR1_TE_BIT 3
+#define USART_CR1_TE_ENABLE (1 << USART_CR1_TE_BIT)
+
+
+#define USART_CR1_RE_BIT 2
+#define USART_CR1_RE_ENABLE (1 << USART_CR1_RE_BIT)
+
+
+#define USART_BRR_MANTISSA_BIT 4
+#define USART_BRR_MANTISSA_MASK (0b111111111111)
+
+#define USART_BRR_FRACTION_BIT 0
+#define USART_BRR_FRACTION_MASK (0b111)
+
+void usart2_init(void);
+void usart2_start(void);
+# 10 "src/main.c" 2
 
 #define exit 42
 
@@ -2313,7 +2393,9 @@ static void system_clock_init(void) {
 int main(void) {
   (void) system_clock_init();
   (void) tim4_init();
+  (void) usart2_init();
 
+  (void) tim4_start();
   (void) tim4_start();
 
   uint16_t led = (((('C') - 'A') << 8) | 13);
@@ -2322,13 +2404,13 @@ int main(void) {
 
   uint16_t counter = ((struct timer *) (0x40000800U))->CNT;
   
-# 87 "src/main.c" 3 4
+# 90 "src/main.c" 3 4
  _Bool 
-# 87 "src/main.c"
+# 90 "src/main.c"
       led_on = 
-# 87 "src/main.c" 3 4
+# 90 "src/main.c" 3 4
                ((_Bool)+0u)
-# 87 "src/main.c"
+# 90 "src/main.c"
                     ;
   while(1) {
  if ((((struct timer *) (0x40000800U))->CNT - counter) >= 250) {