diff --git a/src/rcc.h b/src/rcc.h
new file mode 100644
index 0000000..8f8f09a
--- /dev/null
+++ b/src/rcc.h
@@ -0,0 +1,40 @@
+#ifndef RCC_H_
+#define RCC_H_
+
+#include <inttypes.h>
+
+struct rcc {
+  volatile uint32_t CR;            // Clock control register
+  volatile uint32_t PLLCFGR;       // PLL configuration register
+  volatile uint32_t CFGR;          // Clock configuration register
+  volatile uint32_t CIR;           // Clock interrupt register
+  volatile uint32_t AHB1RSTR;      // AHB1 peripheral reset register
+  volatile uint32_t AHB2RSTR;      // AHB2 peripheral reset register
+  volatile uint32_t RESERVED0[2];  // Reserved (padding)
+  volatile uint32_t APB1RSTR;      // APB1 peripheral reset register
+  volatile uint32_t APB2RSTR;      // APB2 peripheral reset register
+  volatile uint32_t RESERVED1[2];  // Reserved (padding)
+  volatile uint32_t AHB1ENR;       // AHB1 peripheral clock enable register
+  volatile uint32_t AHB2ENR;       // AHB2 peripheral clock enable register
+  volatile uint32_t RESERVED2[2];  // Reserved (padding)
+  volatile uint32_t APB1ENR;       // APB1 peripheral clock enable register
+  volatile uint32_t APB2ENR;       // APB2 peripheral clock enable register
+  volatile uint32_t RESERVED3[2];  // Reserved (padding)
+  volatile uint32_t AHB1LPENR;     // AHB1 peripheral clock enable in low power mode register
+  volatile uint32_t AHB2LPENR;     // AHB2 peripheral clock enable in low power mode register
+  volatile uint32_t RESERVED4[2];  // Reserved (padding)
+  volatile uint32_t APB1LPENR;     // APB1 peripheral clock enable in low power mode register
+  volatile uint32_t APB2LPENR;     // APB2 peripheral clock enable in low power mode register
+  volatile uint32_t RESERVED5[2];  // Reserved (padding)
+  volatile uint32_t BDCR;          // Backup domain control register
+  volatile uint32_t CSR;           // Clock control & status register
+  volatile uint32_t RESERVED6[2];  // Reserved (padding)
+  volatile uint32_t SSCGR;         // Spread spectrum clock generation register
+  volatile uint32_t PLLI2SCFGR;    // PLLI2S configuration register
+  volatile uint32_t DCKCFGR;       // Dedicated clocks configuration register
+};
+
+#define RCC_BASE_ADDR (0x40023800U)
+#define RCC ((struct rcc *) RCC_BASE_ADDR)
+
+#endif