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Configure system clock to run at 96Mhz

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This commit is contained in:
Alexander Heldt
2024-07-31 11:57:35 +02:00
parent 0fec3d6a6c
commit d9389b4eb8
9 changed files with 1252 additions and 527 deletions
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BIN
build/final.elf
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262
build/final.elf.map
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@@ -33,6 +33,8 @@ Discarded input sections
.group 0x00000000 0xc build/main.o .group 0x00000000 0xc build/main.o
.group 0x00000000 0xc build/main.o .group 0x00000000 0xc build/main.o
.group 0x00000000 0xc build/main.o .group 0x00000000 0xc build/main.o
.group 0x00000000 0xc build/main.o
.group 0x00000000 0xc build/main.o
.text 0x00000000 0x0 build/main.o .text 0x00000000 0x0 build/main.o
.data 0x00000000 0x0 build/main.o .data 0x00000000 0x0 build/main.o
.bss 0x00000000 0x0 build/main.o .bss 0x00000000 0x0 build/main.o
@@ -86,7 +88,7 @@ LOAD build/startup.o
0x08000000 interrupt_vector_table 0x08000000 interrupt_vector_table
0x08000198 . = ALIGN (0x4) 0x08000198 . = ALIGN (0x4)
.text 0x08000198 0x1a8 .text 0x08000198 0x2f4
0x08000198 . = ALIGN (0x4) 0x08000198 . = ALIGN (0x4)
*(.text) *(.text)
*(.text.*) *(.text.*)
@@ -96,108 +98,112 @@ LOAD build/startup.o
.text.gpio_write .text.gpio_write
0x080001fa 0x4c build/gpio.o 0x080001fa 0x4c build/gpio.o
0x080001fa gpio_write 0x080001fa gpio_write
.text.spin 0x08000246 0x22 build/main.o *fill* 0x08000246 0x2
.text.main 0x08000268 0x5c build/main.o .text.system_clock_init
0x08000268 main 0x08000248 0x144 build/main.o
.text.spin 0x0800038c 0x22 build/main.o
*fill* 0x080003ae 0x2
.text.main 0x080003b0 0x60 build/main.o
0x080003b0 main
.text.init_memory .text.init_memory
0x080002c4 0x64 build/startup.o 0x08000410 0x64 build/startup.o
0x080002c4 init_memory 0x08000410 init_memory
.text.reset 0x08000328 0x10 build/startup.o .text.reset 0x08000474 0x10 build/startup.o
0x08000328 reset 0x08000474 reset
.text.default_handler .text.default_handler
0x08000338 0x8 build/startup.o 0x08000484 0x8 build/startup.o
0x08000338 exti0 0x08000484 exti0
0x08000338 debug_monitor 0x08000484 debug_monitor
0x08000338 rcc 0x08000484 rcc
0x08000338 x 0x08000484 x
0x08000338 sdio 0x08000484 sdio
0x08000338 usage_fault 0x08000484 usage_fault
0x08000338 tim1_up_tim10 0x08000484 tim1_up_tim10
0x08000338 usart1 0x08000484 usart1
0x08000338 i2c3_er 0x08000484 i2c3_er
0x08000338 spi2 0x08000484 spi2
0x08000338 dma1_stream1 0x08000484 dma1_stream1
0x08000338 bus_fault 0x08000484 bus_fault
0x08000338 spi5 0x08000484 spi5
0x08000338 exti3 0x08000484 exti3
0x08000338 dma2_stream5 0x08000484 dma2_stream5
0x08000338 tim2 0x08000484 tim2
0x08000338 dma1_stream6 0x08000484 dma1_stream6
0x08000338 default_handler 0x08000484 default_handler
0x08000338 i2c1_er 0x08000484 i2c1_er
0x08000338 hard_fault 0x08000484 hard_fault
0x08000338 usart6 0x08000484 usart6
0x08000338 exti15_10 0x08000484 exti15_10
0x08000338 usart2 0x08000484 usart2
0x08000338 pend_sv 0x08000484 pend_sv
0x08000338 i2c1_ev 0x08000484 i2c1_ev
0x08000338 wwdg 0x08000484 wwdg
0x08000338 adc 0x08000484 adc
0x08000338 rtc_alarm 0x08000484 rtc_alarm
0x08000338 spi3 0x08000484 spi3
0x08000338 exti1 0x08000484 exti1
0x08000338 mem_manage 0x08000484 mem_manage
0x08000338 dma2_stream1 0x08000484 dma2_stream1
0x08000338 dma1_stream2 0x08000484 dma1_stream2
0x08000338 dma2_stream3 0x08000484 dma2_stream3
0x08000338 sv_call 0x08000484 sv_call
0x08000338 tim3 0x08000484 tim3
0x08000338 otg_fs 0x08000484 otg_fs
0x08000338 dma1_stream5 0x08000484 dma1_stream5
0x08000338 dma2_stream6 0x08000484 dma2_stream6
0x08000338 flash 0x08000484 flash
0x08000338 tamp_stamp 0x08000484 tamp_stamp
0x08000338 i2c3_ev 0x08000484 i2c3_ev
0x08000338 rtc_wkup 0x08000484 rtc_wkup
0x08000338 dma2_stream0 0x08000484 dma2_stream0
0x08000338 pvd 0x08000484 pvd
0x08000338 fpu 0x08000484 fpu
0x08000338 exti4 0x08000484 exti4
0x08000338 exti2 0x08000484 exti2
0x08000338 spi1 0x08000484 spi1
0x08000338 dma1_stream0 0x08000484 dma1_stream0
0x08000338 tim1_brk_tim9 0x08000484 tim1_brk_tim9
0x08000338 i2c2_ev 0x08000484 i2c2_ev
0x08000338 otg_fs_wkup 0x08000484 otg_fs_wkup
0x08000338 spi4 0x08000484 spi4
0x08000338 dma2_stream2 0x08000484 dma2_stream2
0x08000338 tim1_cc 0x08000484 tim1_cc
0x08000338 tim1_trg_com_tim11 0x08000484 tim1_trg_com_tim11
0x08000338 exti9_5 0x08000484 exti9_5
0x08000338 dma1_stream3 0x08000484 dma1_stream3
0x08000338 dma2_stream4 0x08000484 dma2_stream4
0x08000338 i2c2_er 0x08000484 i2c2_er
0x08000338 dma2_stream7 0x08000484 dma2_stream7
0x08000338 dma1_stream7 0x08000484 dma1_stream7
0x08000338 nmi 0x08000484 nmi
0x08000338 systick 0x08000484 systick
0x08000338 tim4 0x08000484 tim4
0x08000338 tim5 0x08000484 tim5
0x08000338 dma1_stream4 0x08000484 dma1_stream4
*(.rodata) *(.rodata)
*(.rodata.*) *(.rodata.*)
0x08000340 . = ALIGN (0x4) 0x0800048c . = ALIGN (0x4)
0x08000340 _data_addr = LOADADDR (.data) 0x0800048c _data_addr = LOADADDR (.data)
.glue_7 0x08000340 0x0 .glue_7 0x0800048c 0x0
.glue_7 0x08000340 0x0 linker stubs .glue_7 0x0800048c 0x0 linker stubs
.glue_7t 0x08000340 0x0 .glue_7t 0x0800048c 0x0
.glue_7t 0x08000340 0x0 linker stubs .glue_7t 0x0800048c 0x0 linker stubs
.vfp11_veneer 0x08000340 0x0 .vfp11_veneer 0x0800048c 0x0
.vfp11_veneer 0x08000340 0x0 linker stubs .vfp11_veneer 0x0800048c 0x0 linker stubs
.v4_bx 0x08000340 0x0 .v4_bx 0x0800048c 0x0
.v4_bx 0x08000340 0x0 linker stubs .v4_bx 0x0800048c 0x0 linker stubs
.iplt 0x08000340 0x0 .iplt 0x0800048c 0x0
.iplt 0x08000340 0x0 build/main.o .iplt 0x0800048c 0x0 build/main.o
.rel.dyn 0x08000340 0x0 .rel.dyn 0x0800048c 0x0
.rel.iplt 0x08000340 0x0 build/main.o .rel.iplt 0x0800048c 0x0 build/main.o
.data 0x20000000 0x0 load address 0x08000340 .data 0x20000000 0x0 load address 0x0800048c
0x20000000 . = ALIGN (0x4) 0x20000000 . = ALIGN (0x4)
0x20000000 _data_start = . 0x20000000 _data_start = .
*(.data) *(.data)
@@ -205,10 +211,10 @@ LOAD build/startup.o
0x20000000 . = ALIGN (0x4) 0x20000000 . = ALIGN (0x4)
0x20000000 _data_end = . 0x20000000 _data_end = .
.igot.plt 0x20000000 0x0 load address 0x08000340 .igot.plt 0x20000000 0x0 load address 0x0800048c
.igot.plt 0x20000000 0x0 build/main.o .igot.plt 0x20000000 0x0 build/main.o
.bss 0x20000000 0x0 load address 0x08000340 .bss 0x20000000 0x0 load address 0x0800048c
0x20000000 . = ALIGN (0x4) 0x20000000 . = ALIGN (0x4)
0x20000000 _bss_start = . 0x20000000 _bss_start = .
*(.bss) *(.bss)
@@ -218,34 +224,34 @@ LOAD build/startup.o
OUTPUT(build/final.elf elf32-littlearm) OUTPUT(build/final.elf elf32-littlearm)
LOAD linker stubs LOAD linker stubs
.debug_info 0x00000000 0x64e .debug_info 0x00000000 0x6f5
.debug_info 0x00000000 0x21a build/gpio.o .debug_info 0x00000000 0x21a build/gpio.o
.debug_info 0x0000021a 0x2ac build/main.o .debug_info 0x0000021a 0x353 build/main.o
.debug_info 0x000004c6 0x188 build/startup.o .debug_info 0x0000056d 0x188 build/startup.o
.debug_abbrev 0x00000000 0x36d .debug_abbrev 0x00000000 0x397
.debug_abbrev 0x00000000 0x12b build/gpio.o .debug_abbrev 0x00000000 0x12b build/gpio.o
.debug_abbrev 0x0000012b 0x11b build/main.o .debug_abbrev 0x0000012b 0x145 build/main.o
.debug_abbrev 0x00000246 0x127 build/startup.o .debug_abbrev 0x00000270 0x127 build/startup.o
.debug_aranges 0x00000000 0x80 .debug_aranges 0x00000000 0x88
.debug_aranges .debug_aranges
0x00000000 0x28 build/gpio.o 0x00000000 0x28 build/gpio.o
.debug_aranges .debug_aranges
0x00000028 0x28 build/main.o 0x00000028 0x30 build/main.o
.debug_aranges .debug_aranges
0x00000050 0x30 build/startup.o 0x00000058 0x30 build/startup.o
.debug_rnglists .debug_rnglists
0x00000000 0x51 0x00000000 0x58
.debug_rnglists .debug_rnglists
0x00000000 0x19 build/gpio.o 0x00000000 0x19 build/gpio.o
.debug_rnglists .debug_rnglists
0x00000019 0x19 build/main.o 0x00000019 0x20 build/main.o
.debug_rnglists .debug_rnglists
0x00000032 0x1f build/startup.o 0x00000039 0x1f build/startup.o
.debug_macro 0x00000000 0x2e91 .debug_macro 0x00000000 0x2f1d
.debug_macro 0x00000000 0xb56 build/gpio.o .debug_macro 0x00000000 0xb56 build/gpio.o
.debug_macro 0x00000b56 0x22 build/gpio.o .debug_macro 0x00000b56 0x22 build/gpio.o
.debug_macro 0x00000b78 0x75 build/gpio.o .debug_macro 0x00000b78 0x75 build/gpio.o
@@ -261,24 +267,26 @@ LOAD linker stubs
.debug_macro 0x00001115 0x4cc build/gpio.o .debug_macro 0x00001115 0x4cc build/gpio.o
.debug_macro 0x000015e1 0x22 build/gpio.o .debug_macro 0x000015e1 0x22 build/gpio.o
.debug_macro 0x00001603 0x34 build/gpio.o .debug_macro 0x00001603 0x34 build/gpio.o
.debug_macro 0x00001637 0xb6b build/main.o .debug_macro 0x00001637 0xb7d build/main.o
.debug_macro 0x000021a2 0x118 build/main.o .debug_macro 0x000021b4 0x11e build/main.o
.debug_macro 0x000022ba 0x2e build/main.o .debug_macro 0x000022d2 0x2e build/main.o
.debug_macro 0x000022e8 0xb02 build/startup.o .debug_macro 0x00002300 0x46 build/main.o
.debug_macro 0x00002dea 0x56 build/startup.o .debug_macro 0x00002346 0x2e build/main.o
.debug_macro 0x00002e40 0x51 build/startup.o .debug_macro 0x00002374 0xb02 build/startup.o
.debug_macro 0x00002e76 0x56 build/startup.o
.debug_macro 0x00002ecc 0x51 build/startup.o
.debug_line 0x00000000 0x2fe .debug_line 0x00000000 0x3ee
.debug_line 0x00000000 0x116 build/gpio.o .debug_line 0x00000000 0x116 build/gpio.o
.debug_line 0x00000116 0xfe build/main.o .debug_line 0x00000116 0x1ee build/main.o
.debug_line 0x00000214 0xea build/startup.o .debug_line 0x00000304 0xea build/startup.o
.debug_str 0x00000000 0x5ada .debug_str 0x00000000 0x5d86
.debug_str 0x00000000 0x5372 build/gpio.o .debug_str 0x00000000 0x5372 build/gpio.o
0x551a (size before relaxing) 0x551a (size before relaxing)
.debug_str 0x00005372 0x6e0 build/main.o .debug_str 0x00005372 0x98c build/main.o
0x5ba5 (size before relaxing) 0x5e56 (size before relaxing)
.debug_str 0x00005a52 0x88 build/startup.o .debug_str 0x00005cfe 0x88 build/startup.o
0x3cdf (size before relaxing) 0x3cdf (size before relaxing)
.comment 0x00000000 0x45 .comment 0x00000000 0x45
@@ -297,18 +305,18 @@ LOAD linker stubs
0x00000068 0x34 build/startup.o 0x00000068 0x34 build/startup.o
.debug_line_str .debug_line_str
0x00000000 0x265 0x00000000 0x273
.debug_line_str .debug_line_str
0x00000000 0x24e build/gpio.o 0x00000000 0x24e build/gpio.o
0x260 (size before relaxing) 0x260 (size before relaxing)
.debug_line_str .debug_line_str
0x0000024e 0xd build/main.o 0x0000024e 0x1b build/main.o
0x266 (size before relaxing) 0x274 (size before relaxing)
.debug_line_str .debug_line_str
0x0000025b 0xa build/startup.o 0x00000269 0xa build/startup.o
0x21b (size before relaxing) 0x21b (size before relaxing)
.debug_frame 0x00000000 0x124 .debug_frame 0x00000000 0x144
.debug_frame 0x00000000 0x60 build/gpio.o .debug_frame 0x00000000 0x60 build/gpio.o
.debug_frame 0x00000060 0x58 build/main.o .debug_frame 0x00000060 0x78 build/main.o
.debug_frame 0x000000b8 0x6c build/startup.o .debug_frame 0x000000d8 0x6c build/startup.o

1264
build/main.S
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File diff suppressed because it is too large Load Diff

146
build/main.i
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@@ -2012,14 +2012,9 @@ struct rcc {
#define RCC_CR_PLLON_BIT 24 #define RCC_CR_PLLON_BIT 24
#define RCC_CR_PLLON_OFF (0 << RCC_CR_PLLON_BIT)
#define RCC_CR_PLLON_ON (1 << RCC_CR_PLLON_BIT) #define RCC_CR_PLLON_ON (1 << RCC_CR_PLLON_BIT)
#define RCC_CR_HSEBYP_BIT 18
#define RCC_CR_HSEBYP (1 << RCC_CR_HSEBYP_BIT)
#define RCC_CR_HSERDY_BIT 17 #define RCC_CR_HSERDY_BIT 17
#define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT) #define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT)
@@ -2027,8 +2022,13 @@ struct rcc {
#define RCC_CR_HSEON_BIT 16 #define RCC_CR_HSEON_BIT 16
#define RCC_CR_HSEON_ON (1 << RCC_CR_HSEON_BIT) #define RCC_CR_HSEON_ON (1 << RCC_CR_HSEON_BIT)
#define RCC_CR_HSIRDY_BIT 1
#define RCC_CR_HSIRDY_READY (1 << RCC_CR_HSIRDY_BIT)
#define RCC_CR_HSION_BIT 0 #define RCC_CR_HSION_BIT 0
#define RCC_CR_HSION_OFF (0 << RCC_CR_HSION_BIT) #define RCC_CR_HSION_ON (1 << RCC_CR_HSION_BIT)
#define RCC_PLLCFGR_PLLQ_BIT 24 #define RCC_PLLCFGR_PLLQ_BIT 24
@@ -2081,6 +2081,10 @@ struct rcc {
#define RCC_CFGR_SW_BIT 0 #define RCC_CFGR_SW_BIT 0
#define RCC_CFGR_SW_MASK (0b11) #define RCC_CFGR_SW_MASK (0b11)
#define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT) #define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT)
#define RCC_APB1ENR_PWREN_BIT 28
#define RCC_APB1ENR_PWREN_CLOCK_ENABLE (1 << RCC_APB1ENR_PWREN_BIT)
# 3 "src/main.c" 2 # 3 "src/main.c" 2
# 1 "src/gpio.h" 1 # 1 "src/gpio.h" 1
@@ -2140,28 +2144,150 @@ void gpio_write(uint16_t pin,
# 40 "src/gpio.h" # 40 "src/gpio.h"
val); val);
# 4 "src/main.c" 2 # 4 "src/main.c" 2
# 1 "src/flash.h" 1
#define FLASH_H_
struct flash {
volatile uint32_t ACR;
volatile uint32_t KEYR;
volatile uint32_t OPTKEYR;
volatile uint32_t SR;
volatile uint32_t CR;
volatile uint32_t OPTCR;
};
#define FLASH_BASE_ADDR (0x40023C00U)
#define FLASH ((struct flash *) FLASH_BASE_ADDR)
#define FLASH_ACR_DCEN_BIT 10
#define FLASH_ACR_DCEN_ENABLE (1 <<FLASH_ACR_DCEN_BIT)
#define FLASH_ACR_ICEN_BIT 9
#define FLASH_ACR_ICEN_ENABLE (1 <<FLASH_ACR_ICEN_BIT)
#define FLASH_ACR_LATENCY_3_WAIT_STATES (0x0111)
#define FLASH_ACR_LATENCY_BIT 0
#define FLASH_ACR_LATENCY_MASK (0b1111)
#define FLASH_ACR_LATENCY(latency) ((latency & FLASH_ACR_LATENCY_MASK) << FLASH_ACR_LATENCY_BIT)
# 5 "src/main.c" 2
# 1 "src/pwr.h" 1
#define PWR_H_
struct pwr {
volatile uint32_t CR;
volatile uint32_t CSR;
};
#define PWR_BASE_ADDR (0x40007000U)
#define PWR ((struct pwr *) PWR_BASE_ADDR)
#define PWR_SCALE3 (0b11)
#define PWR_CR_VOS_BIT 14
#define PWR_CR_VOS_MASK (0b11)
#define PWR_CR_VOS(scale) ((scale & PWR_CR_VOS_MASK) << PWR_CR_VOS_BIT)
# 6 "src/main.c" 2
#define exit 42 #define exit 42
static void system_clock_init(void) {
((struct rcc *) (0x40023800U))->APB1ENR |= (1 << 28);
((struct pwr *) (0x40007000U))->CR &= ~((0b11) << 14);
((struct pwr *) (0x40007000U))->CR |= ((0b11) << 14);
((struct rcc *) (0x40023800U))->CR |= (1 << 16);
while (!(((struct rcc *) (0x40023800U))->CR & (1 << 17)));
((struct rcc *) (0x40023800U))->CR &= ~(1 << 24);
((struct rcc *) (0x40023800U))->PLLCFGR |= (1 << 22);
((struct rcc *) (0x40023800U))->PLLCFGR |= ((25 & (0b111111)) << 0) | ((196 & (0b111111111)) << 6) | ((2 & (0b11)) << 16) | ((4 & (0b1111)) << 24);
((struct rcc *) (0x40023800U))->CFGR &= ~((0b1111) << 4);
((struct rcc *) (0x40023800U))->CFGR |= (0 << 4);
((struct rcc *) (0x40023800U))->CFGR &= ~((0b111) << 10);
((struct rcc *) (0x40023800U))->CFGR |= ((0b100) << 10);
((struct rcc *) (0x40023800U))->CFGR &= ~((0b111) << 13);
((struct rcc *) (0x40023800U))->CFGR |= (0 << 13);
((struct rcc *) (0x40023800U))->CR |= (1 << 24);
while (!(((struct rcc *) (0x40023800U))->CR & (1 << 17)));
((struct flash *) (0x40023C00U))->ACR |= (1 <<10);
((struct flash *) (0x40023C00U))->ACR |= (1 <<9);
((struct flash *) (0x40023C00U))->ACR &= ~((0b1111) << 0);
((struct rcc *) (0x40023800U))->CFGR |= ((0x0111) << 0);
((struct rcc *) (0x40023800U))->CFGR &= ~((0b11) << 0);
((struct rcc *) (0x40023800U))->CFGR |= ((0b10) << 0);
while (((((struct rcc *) (0x40023800U))->CFGR >> 2) & (0b11)) != (0b10));
((struct rcc *) (0x40023800U))->CR &= ~(1 << 0);
}
static inline void spin(volatile uint32_t count) { static inline void spin(volatile uint32_t count) {
while (count--) (void) 0; while (count--) (void) 0;
} }
int main(void) { int main(void) {
(void) system_clock_init();
uint16_t led = (((('C') - 'A') << 8) | 13); uint16_t led = (((('C') - 'A') << 8) | 13);
((struct rcc *) (0x40023800U))->AHB1ENR |= (1 << (led >> 8)); ((struct rcc *) (0x40023800U))->AHB1ENR |= (1 << (led >> 8));
gpio_set_mode(led, GPIO_MODE_OUTPUT); gpio_set_mode(led, GPIO_MODE_OUTPUT);
for (;;) { for (;;) {
gpio_write(led, gpio_write(led,
# 16 "src/main.c" 3 4 # 84 "src/main.c" 3 4
((_Bool)+1u) ((_Bool)+1u)
# 16 "src/main.c" # 84 "src/main.c"
); );
spin(999999); spin(999999);
gpio_write(led, gpio_write(led,
# 18 "src/main.c" 3 4 # 86 "src/main.c" 3 4
((_Bool)+0u) ((_Bool)+0u)
# 18 "src/main.c" # 86 "src/main.c"
); );
spin(999999); spin(999999);
}; };

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build/main.o
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1
src/flash.h
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@@ -17,7 +17,6 @@ struct flash {
// ACR Register // ACR Register
// Data cache enable // Data cache enable
#define FLASH_ACR_DCEN_BIT 10 #define FLASH_ACR_DCEN_BIT 10
#define FLASH_ACR_DCEN_ENABLE (1 <<FLASH_ACR_DCEN_BIT) #define FLASH_ACR_DCEN_ENABLE (1 <<FLASH_ACR_DCEN_BIT)

68
src/main.c
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@@ -1,14 +1,82 @@
#include <inttypes.h> #include <inttypes.h>
#include "rcc.h" #include "rcc.h"
#include "gpio.h" #include "gpio.h"
#include "flash.h"
#include "pwr.h"
#define exit 42 #define exit 42
static void system_clock_init(void) {
// Power on clock for PLL
RCC->APB1ENR |= RCC_APB1ENR_PWREN_CLOCK_ENABLE;
// Set voltage scaling to "high"
PWR->CR &= ~(PWR_CR_VOS_MASK << PWR_CR_VOS_BIT);
PWR->CR |= (PWR_SCALE3 << PWR_CR_VOS_BIT);
// Turn on HSE
RCC->CR |= RCC_CR_HSEON_ON;
// Wait indefinitely for HSE to be ready
// TODO indicate error/timeout somehow?
while (!(RCC->CR & RCC_CR_HSERDY_READY));
// Disable PLL before changing settings as documentation state
// "These bits should be written only if PLL is disabled."
RCC->CR &= ~RCC_CR_PLLON_ON;
// Set HSE as PLL source
RCC->PLLCFGR |= RCC_PLLCFGR_PLLSRC_HSE;
// Settings to achieve system clock of 96Mhz
RCC->PLLCFGR |= RCC_PLLCFGR_PLLM(25) | RCC_PLLCFGR_PLLN(196) | RCC_PLLCFGR_PLLP(2) | RCC_PLLCFGR_PLLQ(4);
// Set AHB prescalar to /1
RCC->CFGR &= ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_BIT);
RCC->CFGR |= (RCC_CFGR_HPRE_DIV_NONE << RCC_CFGR_HPRE_BIT);
// Set APB1 prescalar to /2
RCC->CFGR &= ~(RCC_CFGR_PPRE1_MASK << RCC_CFGR_PPRE1_BIT);
RCC->CFGR |= (RCC_CFGR_PPRE_DIV_2 << RCC_CFGR_PPRE1_BIT);
// Set APB2 prescalar to /1
RCC->CFGR &= ~(RCC_CFGR_PPRE2_MASK << RCC_CFGR_PPRE2_BIT);
RCC->CFGR |= (RCC_CFGR_PPRE_DIV_NONE << RCC_CFGR_PPRE2_BIT);
// Turn PLL back on
RCC->CR |= RCC_CR_PLLON_ON;
// Wait indefinitely for PLL to be ready
// TODO indicate error/timeout somehow?
while (!(RCC->CR & RCC_CR_HSERDY_READY));
// Enable caching of instructions and data
FLASH->ACR |= FLASH_ACR_DCEN_ENABLE;
FLASH->ACR |= FLASH_ACR_ICEN_ENABLE;
// Set latency to be 3 wait states (TODO: understand why exactly 3)
FLASH->ACR &= ~(FLASH_ACR_LATENCY_MASK << FLASH_ACR_LATENCY_BIT);
RCC->CFGR |= (FLASH_ACR_LATENCY_3_WAIT_STATES << FLASH_ACR_LATENCY_BIT);
// Use PLL as system clock
RCC->CFGR &= ~(RCC_CFGR_SW_MASK << RCC_CFGR_SW_BIT);
RCC->CFGR |= (RCC_CFGR_SW_PLL << RCC_CFGR_SW_BIT);
// Wait indefinitely for PLL clock to be selected
// TODO indicate error/timeout somehow?
while (((RCC->CFGR >> RCC_CFGR_SWS_BIT) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL);
// Turn off HSI (which is on by default)
RCC->CR &= ~RCC_CR_HSION_ON;
}
static inline void spin(volatile uint32_t count) { static inline void spin(volatile uint32_t count) {
while (count--) (void) 0; while (count--) (void) 0;
} }
int main(void) { int main(void) {
(void) system_clock_init();
uint16_t led = PIN('C', 13); // Blue LED uint16_t led = PIN('C', 13); // Blue LED
RCC->AHB1ENR |= BIT(PINPORT(led)); // Enable GPIO clock for LED RCC->AHB1ENR |= BIT(PINPORT(led)); // Enable GPIO clock for LED
gpio_set_mode(led, GPIO_MODE_OUTPUT); // Set blue LED to output mode gpio_set_mode(led, GPIO_MODE_OUTPUT); // Set blue LED to output mode

22
src/pwr.h Normal file
View File

@@ -0,0 +1,22 @@
#ifndef PWR_H_
#define PWR_H_
#include <inttypes.h>
struct pwr {
volatile uint32_t CR; // Power control register
volatile uint32_t CSR; // Power control/status registe
};
#define PWR_BASE_ADDR (0x40007000U)
#define PWR ((struct pwr *) PWR_BASE_ADDR)
// Power control register
#define PWR_SCALE3 (0b11)
// Regulator voltage scaling output selection
#define PWR_CR_VOS_BIT 14 // Bits [15:14]
#define PWR_CR_VOS_MASK (0b11)
#define PWR_CR_VOS(scale) ((scale & PWR_CR_VOS_MASK) << PWR_CR_VOS_BIT)
#endif

16
src/rcc.h
View File

@@ -44,13 +44,8 @@ struct rcc {
// PLL toggle // PLL toggle
#define RCC_CR_PLLON_BIT 24 #define RCC_CR_PLLON_BIT 24
#define RCC_CR_PLLON_OFF (0 << RCC_CR_PLLON_BIT)
#define RCC_CR_PLLON_ON (1 << RCC_CR_PLLON_BIT) #define RCC_CR_PLLON_ON (1 << RCC_CR_PLLON_BIT)
// HSE clock bypass
#define RCC_CR_HSEBYP_BIT 18
#define RCC_CR_HSEBYP (1 << RCC_CR_HSEBYP_BIT)
// HSE clock ready flag // HSE clock ready flag
#define RCC_CR_HSERDY_BIT 17 #define RCC_CR_HSERDY_BIT 17
#define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT) #define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT)
@@ -59,8 +54,13 @@ struct rcc {
#define RCC_CR_HSEON_BIT 16 #define RCC_CR_HSEON_BIT 16
#define RCC_CR_HSEON_ON (1 << RCC_CR_HSEON_BIT) #define RCC_CR_HSEON_ON (1 << RCC_CR_HSEON_BIT)
// HSI clock ready flag
#define RCC_CR_HSIRDY_BIT 1
#define RCC_CR_HSIRDY_READY (1 << RCC_CR_HSIRDY_BIT)
// HSI clock enable
#define RCC_CR_HSION_BIT 0 #define RCC_CR_HSION_BIT 0
#define RCC_CR_HSION_OFF (0 << RCC_CR_HSION_BIT) #define RCC_CR_HSION_ON (1 << RCC_CR_HSION_BIT)
// PLLCFGR Register // PLLCFGR Register
#define RCC_PLLCFGR_PLLQ_BIT 24 // Bits [27:24] #define RCC_PLLCFGR_PLLQ_BIT 24 // Bits [27:24]
@@ -114,4 +114,8 @@ struct rcc {
#define RCC_CFGR_SW_MASK (0b11) #define RCC_CFGR_SW_MASK (0b11)
#define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT) #define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT)
// APB1ENR Register
#define RCC_APB1ENR_PWREN_BIT 28
#define RCC_APB1ENR_PWREN_CLOCK_ENABLE (1 << RCC_APB1ENR_PWREN_BIT)
#endif #endif