#ifndef TIMER_H_ #define TIMER_H_ #include struct timer { volatile uint32_t CR1; // Control register 1 volatile uint32_t CR2; // Control register 2 volatile uint32_t SMCR; // Slave mode control register volatile uint32_t DIER; // DMA/interrupt enable registe volatile uint32_t SR; // Status register volatile uint32_t EGR; // Event generation register volatile uint32_t CCMR1; // Capture/compare mode register 1 volatile uint32_t CCMR2; // Capture/compare mode register 2 volatile uint32_t CCER; // Capture/compare enable register volatile uint32_t CNT; // Counter volatile uint32_t PSC; // Prescalar volatile uint32_t ARR; // Auto-reload register volatile uint32_t RCR; // Repetition counter registe volatile uint32_t CCR1; // Capture/compare register 1 volatile uint32_t CCR2; // Capture/compare register 2 volatile uint32_t CCR3; // Capture/compare register 3 volatile uint32_t CCR4; // Capture/compare register 4 volatile uint32_t BDTR; // Break and dead-time register volatile uint32_t DCR; // DMA control register volatile uint32_t DMAR; // DMA address for full transfer }; #define TIM4_BASE_ADDR (0x40000800U) #define TIM4 ((struct timer *) TIM4_BASE_ADDR) #define TIM4_CR_CEN_BIT 0 #define TIM4_ENABLE (1 << TIM4_CR_CEN_BIT) void tim4_init(void); void tim4_start(void); #endif