#ifndef RCC_H_
#define RCC_H_

#include <inttypes.h>

struct rcc {
  volatile uint32_t CR;            // Clock control register
  volatile uint32_t PLLCFGR;       // PLL configuration register
  volatile uint32_t CFGR;          // Clock configuration register
  volatile uint32_t CIR;           // Clock interrupt register
  volatile uint32_t AHB1RSTR;      // AHB1 peripheral reset register
  volatile uint32_t AHB2RSTR;      // AHB2 peripheral reset register
  volatile uint32_t RESERVED0[2];  // Reserved (padding)
  volatile uint32_t APB1RSTR;      // APB1 peripheral reset register
  volatile uint32_t APB2RSTR;      // APB2 peripheral reset register
  volatile uint32_t RESERVED1[2];  // Reserved (padding)
  volatile uint32_t AHB1ENR;       // AHB1 peripheral clock enable register
  volatile uint32_t AHB2ENR;       // AHB2 peripheral clock enable register
  volatile uint32_t RESERVED2[2];  // Reserved (padding)
  volatile uint32_t APB1ENR;       // APB1 peripheral clock enable register
  volatile uint32_t APB2ENR;       // APB2 peripheral clock enable register
  volatile uint32_t RESERVED3[2];  // Reserved (padding)
  volatile uint32_t AHB1LPENR;     // AHB1 peripheral clock enable in low power mode register
  volatile uint32_t AHB2LPENR;     // AHB2 peripheral clock enable in low power mode register
  volatile uint32_t RESERVED4[2];  // Reserved (padding)
  volatile uint32_t APB1LPENR;     // APB1 peripheral clock enable in low power mode register
  volatile uint32_t APB2LPENR;     // APB2 peripheral clock enable in low power mode register
  volatile uint32_t RESERVED5[2];  // Reserved (padding)
  volatile uint32_t BDCR;          // Backup domain control register
  volatile uint32_t CSR;           // Clock control & status register
  volatile uint32_t RESERVED6[2];  // Reserved (padding)
  volatile uint32_t SSCGR;         // Spread spectrum clock generation register
  volatile uint32_t PLLI2SCFGR;    // PLLI2S configuration register
  volatile uint32_t DCKCFGR;       // Dedicated clocks configuration register
};

#define RCC_BASE_ADDR (0x40023800U)
#define RCC ((struct rcc *) RCC_BASE_ADDR)

// CR Register
// PLL ready flag
#define RCC_CR_PLLRDY_BIT 25
#define RCC_CR_PLLRDY_LOCKED (1 << RCC_CR_PLLRDY_BIT)

// PLL toggle
#define RCC_CR_PLLON_BIT 24
#define RCC_CR_PLLON_OFF (0 << RCC_CR_PLLON_BIT)
#define RCC_CR_PLLON_ON  (1 << RCC_CR_PLLON_BIT)

// HSE clock bypass
#define RCC_CR_HSEBYP_BIT 18
#define RCC_CR_HSEBYP (1 << RCC_CR_HSEBYP_BIT)

// HSE clock ready flag
#define RCC_CR_HSERDY_BIT 17
#define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT)

// HSE clock enable
#define RCC_CR_HSEON_BIT 16
#define RCC_CR_HSEON_ON (1 << RCC_CR_HSEON_BIT)

#define RCC_CR_HSION_BIT 0
#define RCC_CR_HSION_OFF (0 << RCC_CR_HSION_BIT)

// PLLCFGR Register
#define RCC_PLLCFGR_PLLQ_BIT 24 // Bits [27:24]
#define RCC_PLLCFGR_PLLQ_MASK (0b1111)
#define RCC_PLLCFGR_PLLQ(q) ((q & RCC_PLLCFGR_PLLQ_MASK) << RCC_PLLCFGR_PLLQ_BIT)

#define RCC_PLLCFGR_PLLSRC_BIT 22
#define RCC_PLLCFGR_PLLSRC_HSE (1 << RCC_PLLCFGR_PLLSRC_BIT)

#define RCC_PLLCFGR_PLLP_BIT 16 // Bits [17:16]
#define RCC_PLLCFGR_PLLP_MASK (0b11)
#define RCC_PLLCFGR_PLLP(p) ((p & RCC_PLLCFGR_PLLP_MASK) << RCC_PLLCFGR_PLLP_BIT)

#define RCC_PLLCFGR_PLLN_BIT 6 // Bits [14:6]
#define RCC_PLLCFGR_PLLN_MASK (0b111111111)
#define RCC_PLLCFGR_PLLN(n) ((n & RCC_PLLCFGR_PLLN_MASK) << RCC_PLLCFGR_PLLN_BIT)

#define RCC_PLLCFGR_PLLM_BIT 0 // Bits [5:0]
#define RCC_PLLCFGR_PLLM_MASK (0b111111)
#define RCC_PLLCFGR_PLLM(m) ((m & RCC_PLLCFGR_PLLM_MASK) << RCC_PLLCFGR_PLLM_BIT)

// CFGR Register
// APB{1,2} prescalar
#define RCC_CFGR_PPRE_DIV_NONE	0
#define RCC_CFGR_PPRE_DIV_2	(0b100)

// APB2
#define RCC_CFGR_PPRE2_BIT 13 // Bits [15:13]
#define RCC_CFGR_PPRE2_MASK (0b111)

// APB1
#define RCC_CFGR_PPRE1_BIT 10 // Bits [12:10]
#define RCC_CFGR_PPRE1_MASK (0b111)

// AHB prescalar
#define RCC_CFGR_HPRE_DIV_NONE 0

#define RCC_CFGR_HPRE_BIT 4 // Bits [7:4]
#define RCC_CFGR_HPRE_MASK (0b1111)

//System clock switch status
#define RCC_CFGR_SWS_PLL (0b10)

#define RCC_CFGR_SWS_BIT 2 // Bits [3:2]
#define RCC_CFGR_SWS_MASK (0b11)

// System clock switch
#define RCC_CFGR_SW_PLL (0b10)

#define RCC_CFGR_SW_BIT 0 // Bits [1:0]
#define RCC_CFGR_SW_MASK (0b11)
#define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT)

#endif