Add clock configuration registers to rcc.h

build/main.i

@@ -2004,6 +2004,83 @@ struct rcc {
 
 #define RCC_BASE_ADDR (0x40023800U)
 #define RCC ((struct rcc *) RCC_BASE_ADDR)
+
+
+
+#define RCC_CR_PLLRDY_BIT 25
+#define RCC_CR_PLLRDY_LOCKED (1 << RCC_CR_PLLRDY_BIT)
+
+
+#define RCC_CR_PLLON_BIT 24
+#define RCC_CR_PLLON_OFF (0 << RCC_CR_PLLON_BIT)
+#define RCC_CR_PLLON_ON (1 << RCC_CR_PLLON_BIT)
+
+
+#define RCC_CR_HSEBYP_BIT 18
+#define RCC_CR_HSEBYP (1 << RCC_CR_HSEBYP_BIT)
+
+
+#define RCC_CR_HSERDY_BIT 17
+#define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT)
+
+
+#define RCC_CR_HSEON_BIT 16
+#define RCC_CR_HSEON_ON (1 << RCC_CR_HSEON_BIT)
+
+#define RCC_CR_HSION_BIT 0
+#define RCC_CR_HSION_OFF (0 << RCC_CR_HSION_BIT)
+
+
+#define RCC_PLLCFGR_PLLQ_BIT 24
+#define RCC_PLLCFGR_PLLQ_MASK (0b1111)
+#define RCC_PLLCFGR_PLLQ(q) ((q & RCC_PLLCFGR_PLLQ_MASK) << RCC_PLLCFGR_PLLQ_BIT)
+
+#define RCC_PLLCFGR_PLLSRC_BIT 22
+#define RCC_PLLCFGR_PLLSRC_HSE (1 << RCC_PLLCFGR_PLLSRC_BIT)
+
+#define RCC_PLLCFGR_PLLP_BIT 16
+#define RCC_PLLCFGR_PLLP_MASK (0b11)
+#define RCC_PLLCFGR_PLLP(p) ((p & RCC_PLLCFGR_PLLP_MASK) << RCC_PLLCFGR_PLLP_BIT)
+
+#define RCC_PLLCFGR_PLLN_BIT 6
+#define RCC_PLLCFGR_PLLN_MASK (0b111111111)
+#define RCC_PLLCFGR_PLLN(n) ((n & RCC_PLLCFGR_PLLN_MASK) << RCC_PLLCFGR_PLLN_BIT)
+
+#define RCC_PLLCFGR_PLLM_BIT 0
+#define RCC_PLLCFGR_PLLM_MASK (0b111111)
+#define RCC_PLLCFGR_PLLM(m) ((m & RCC_PLLCFGR_PLLM_MASK) << RCC_PLLCFGR_PLLM_BIT)
+
+
+
+#define RCC_CFGR_PPRE_DIV_NONE 0
+#define RCC_CFGR_PPRE_DIV_2 (0b100)
+
+
+#define RCC_CFGR_PPRE2_BIT 13
+#define RCC_CFGR_PPRE2_MASK (0b111)
+
+
+#define RCC_CFGR_PPRE1_BIT 10
+#define RCC_CFGR_PPRE1_MASK (0b111)
+
+
+#define RCC_CFGR_HPRE_DIV_NONE 0
+
+#define RCC_CFGR_HPRE_BIT 4
+#define RCC_CFGR_HPRE_MASK (0b1111)
+
+
+#define RCC_CFGR_SWS_PLL (0b10)
+
+#define RCC_CFGR_SWS_BIT 2
+#define RCC_CFGR_SWS_MASK (0b11)
+
+
+#define RCC_CFGR_SW_PLL (0b10)
+
+#define RCC_CFGR_SW_BIT 0
+#define RCC_CFGR_SW_MASK (0b11)
+#define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT)
 # 3 "src/main.c" 2
 # 1 "src/gpio.h" 1