Add clock configuration registers to rcc.h

build/final.elf.map

@@ -245,7 +245,7 @@ LOAD linker stubs
  .debug_rnglists
                 0x00000032       0x1f build/startup.o
 
-.debug_macro    0x00000000     0x2d8f
+.debug_macro    0x00000000     0x2e91
  .debug_macro   0x00000000      0xb56 build/gpio.o
  .debug_macro   0x00000b56       0x22 build/gpio.o
  .debug_macro   0x00000b78       0x75 build/gpio.o
@@ -262,23 +262,23 @@ LOAD linker stubs
  .debug_macro   0x000015e1       0x22 build/gpio.o
  .debug_macro   0x00001603       0x34 build/gpio.o
  .debug_macro   0x00001637      0xb6b build/main.o
- .debug_macro   0x000021a2       0x16 build/main.o
- .debug_macro   0x000021b8       0x2e build/main.o
- .debug_macro   0x000021e6      0xb02 build/startup.o
- .debug_macro   0x00002ce8       0x56 build/startup.o
- .debug_macro   0x00002d3e       0x51 build/startup.o
+ .debug_macro   0x000021a2      0x118 build/main.o
+ .debug_macro   0x000022ba       0x2e build/main.o
+ .debug_macro   0x000022e8      0xb02 build/startup.o
+ .debug_macro   0x00002dea       0x56 build/startup.o
+ .debug_macro   0x00002e40       0x51 build/startup.o
 
 .debug_line     0x00000000      0x2fe
  .debug_line    0x00000000      0x116 build/gpio.o
  .debug_line    0x00000116       0xfe build/main.o
  .debug_line    0x00000214       0xea build/startup.o
 
-.debug_str      0x00000000     0x553c
+.debug_str      0x00000000     0x5ada
  .debug_str     0x00000000     0x5372 build/gpio.o
                                0x551a (size before relaxing)
- .debug_str     0x00005372      0x142 build/main.o
-                               0x5607 (size before relaxing)
- .debug_str     0x000054b4       0x88 build/startup.o
+ .debug_str     0x00005372      0x6e0 build/main.o
+                               0x5ba5 (size before relaxing)
+ .debug_str     0x00005a52       0x88 build/startup.o
                                0x3cdf (size before relaxing)
 
 .comment        0x00000000       0x45

build/main.i

@@ -2004,6 +2004,83 @@ struct rcc {
 
 #define RCC_BASE_ADDR (0x40023800U)
 #define RCC ((struct rcc *) RCC_BASE_ADDR)
+
+
+
+#define RCC_CR_PLLRDY_BIT 25
+#define RCC_CR_PLLRDY_LOCKED (1 << RCC_CR_PLLRDY_BIT)
+
+
+#define RCC_CR_PLLON_BIT 24
+#define RCC_CR_PLLON_OFF (0 << RCC_CR_PLLON_BIT)
+#define RCC_CR_PLLON_ON (1 << RCC_CR_PLLON_BIT)
+
+
+#define RCC_CR_HSEBYP_BIT 18
+#define RCC_CR_HSEBYP (1 << RCC_CR_HSEBYP_BIT)
+
+
+#define RCC_CR_HSERDY_BIT 17
+#define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT)
+
+
+#define RCC_CR_HSEON_BIT 16
+#define RCC_CR_HSEON_ON (1 << RCC_CR_HSEON_BIT)
+
+#define RCC_CR_HSION_BIT 0
+#define RCC_CR_HSION_OFF (0 << RCC_CR_HSION_BIT)
+
+
+#define RCC_PLLCFGR_PLLQ_BIT 24
+#define RCC_PLLCFGR_PLLQ_MASK (0b1111)
+#define RCC_PLLCFGR_PLLQ(q) ((q & RCC_PLLCFGR_PLLQ_MASK) << RCC_PLLCFGR_PLLQ_BIT)
+
+#define RCC_PLLCFGR_PLLSRC_BIT 22
+#define RCC_PLLCFGR_PLLSRC_HSE (1 << RCC_PLLCFGR_PLLSRC_BIT)
+
+#define RCC_PLLCFGR_PLLP_BIT 16
+#define RCC_PLLCFGR_PLLP_MASK (0b11)
+#define RCC_PLLCFGR_PLLP(p) ((p & RCC_PLLCFGR_PLLP_MASK) << RCC_PLLCFGR_PLLP_BIT)
+
+#define RCC_PLLCFGR_PLLN_BIT 6
+#define RCC_PLLCFGR_PLLN_MASK (0b111111111)
+#define RCC_PLLCFGR_PLLN(n) ((n & RCC_PLLCFGR_PLLN_MASK) << RCC_PLLCFGR_PLLN_BIT)
+
+#define RCC_PLLCFGR_PLLM_BIT 0
+#define RCC_PLLCFGR_PLLM_MASK (0b111111)
+#define RCC_PLLCFGR_PLLM(m) ((m & RCC_PLLCFGR_PLLM_MASK) << RCC_PLLCFGR_PLLM_BIT)
+
+
+
+#define RCC_CFGR_PPRE_DIV_NONE 0
+#define RCC_CFGR_PPRE_DIV_2 (0b100)
+
+
+#define RCC_CFGR_PPRE2_BIT 13
+#define RCC_CFGR_PPRE2_MASK (0b111)
+
+
+#define RCC_CFGR_PPRE1_BIT 10
+#define RCC_CFGR_PPRE1_MASK (0b111)
+
+
+#define RCC_CFGR_HPRE_DIV_NONE 0
+
+#define RCC_CFGR_HPRE_BIT 4
+#define RCC_CFGR_HPRE_MASK (0b1111)
+
+
+#define RCC_CFGR_SWS_PLL (0b10)
+
+#define RCC_CFGR_SWS_BIT 2
+#define RCC_CFGR_SWS_MASK (0b11)
+
+
+#define RCC_CFGR_SW_PLL (0b10)
+
+#define RCC_CFGR_SW_BIT 0
+#define RCC_CFGR_SW_MASK (0b11)
+#define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT)
 # 3 "src/main.c" 2
 # 1 "src/gpio.h" 1
 

src/rcc.h

@@ -37,4 +37,81 @@ struct rcc {
 #define RCC_BASE_ADDR (0x40023800U)
 #define RCC ((struct rcc *) RCC_BASE_ADDR)
 
+// CR Register
+// PLL ready flag
+#define RCC_CR_PLLRDY_BIT 25
+#define RCC_CR_PLLRDY_LOCKED (1 << RCC_CR_PLLRDY_BIT)
+
+// PLL toggle
+#define RCC_CR_PLLON_BIT 24
+#define RCC_CR_PLLON_OFF (0 << RCC_CR_PLLON_BIT)
+#define RCC_CR_PLLON_ON  (1 << RCC_CR_PLLON_BIT)
+
+// HSE clock bypass
+#define RCC_CR_HSEBYP_BIT 18
+#define RCC_CR_HSEBYP (1 << RCC_CR_HSEBYP_BIT)
+
+// HSE clock ready flag
+#define RCC_CR_HSERDY_BIT 17
+#define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT)
+
+// HSE clock enable
+#define RCC_CR_HSEON_BIT 16
+#define RCC_CR_HSEON_ON (1 << RCC_CR_HSEON_BIT)
+
+#define RCC_CR_HSION_BIT 0
+#define RCC_CR_HSION_OFF (0 << RCC_CR_HSION_BIT)
+
+// PLLCFGR Register
+#define RCC_PLLCFGR_PLLQ_BIT 24 // Bits [27:24]
+#define RCC_PLLCFGR_PLLQ_MASK (0b1111)
+#define RCC_PLLCFGR_PLLQ(q) ((q & RCC_PLLCFGR_PLLQ_MASK) << RCC_PLLCFGR_PLLQ_BIT)
+
+#define RCC_PLLCFGR_PLLSRC_BIT 22
+#define RCC_PLLCFGR_PLLSRC_HSE (1 << RCC_PLLCFGR_PLLSRC_BIT)
+
+#define RCC_PLLCFGR_PLLP_BIT 16 // Bits [17:16]
+#define RCC_PLLCFGR_PLLP_MASK (0b11)
+#define RCC_PLLCFGR_PLLP(p) ((p & RCC_PLLCFGR_PLLP_MASK) << RCC_PLLCFGR_PLLP_BIT)
+
+#define RCC_PLLCFGR_PLLN_BIT 6 // Bits [14:6]
+#define RCC_PLLCFGR_PLLN_MASK (0b111111111)
+#define RCC_PLLCFGR_PLLN(n) ((n & RCC_PLLCFGR_PLLN_MASK) << RCC_PLLCFGR_PLLN_BIT)
+
+#define RCC_PLLCFGR_PLLM_BIT 0 // Bits [5:0]
+#define RCC_PLLCFGR_PLLM_MASK (0b111111)
+#define RCC_PLLCFGR_PLLM(m) ((m & RCC_PLLCFGR_PLLM_MASK) << RCC_PLLCFGR_PLLM_BIT)
+
+// CFGR Register
+// APB{1,2} prescalar
+#define RCC_CFGR_PPRE_DIV_NONE	0
+#define RCC_CFGR_PPRE_DIV_2	(0b100)
+
+// APB2
+#define RCC_CFGR_PPRE2_BIT 13 // Bits [15:13]
+#define RCC_CFGR_PPRE2_MASK (0b111)
+
+// APB1
+#define RCC_CFGR_PPRE1_BIT 10 // Bits [12:10]
+#define RCC_CFGR_PPRE1_MASK (0b111)
+
+// AHB prescalar
+#define RCC_CFGR_HPRE_DIV_NONE 0
+
+#define RCC_CFGR_HPRE_BIT 4 // Bits [7:4]
+#define RCC_CFGR_HPRE_MASK (0b1111)
+
+//System clock switch status
+#define RCC_CFGR_SWS_PLL (0b10)
+
+#define RCC_CFGR_SWS_BIT 2 // Bits [3:2]
+#define RCC_CFGR_SWS_MASK (0b11)
+
+// System clock switch
+#define RCC_CFGR_SW_PLL (0b10)
+
+#define RCC_CFGR_SW_BIT 0 // Bits [1:0]
+#define RCC_CFGR_SW_MASK (0b11)
+#define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT)
+
 #endif