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wip why does HSE run at 16MHz?

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This commit is contained in:
Alexander Heldt
2024-12-28 15:03:49 +01:00
parent 4adddddd83
commit 2f4d38a0d8
20 changed files with 1921 additions and 1504 deletions
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build/usart.i
+47 -13
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@@ -2014,6 +2014,11 @@ struct rcc {
#define RCC_CR_PLLON_ON (1 << RCC_CR_PLLON_BIT)
#define RCC_CR_CSS_BIT 19
#define RCC_CR_CSS_ON (1 << RCC_CR_CSS_BIT)
#define RCC_CR_HSERDY_BIT 17
#define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT)
@@ -2036,6 +2041,7 @@ struct rcc {
#define RCC_PLLCFGR_PLLSRC_BIT 22
#define RCC_PLLCFGR_PLLSRC_HSE (1 << RCC_PLLCFGR_PLLSRC_BIT)
#define RCC_PLLCFGR_PLLSRC_HSI (0 << RCC_PLLCFGR_PLLSRC_BIT)
#define RCC_PLLCFGR_PLLP_BIT 16
#define RCC_PLLCFGR_PLLP_MASK (0b11)
@@ -2055,6 +2061,19 @@ struct rcc {
#define RCC_CFGR_PPRE_DIV_2 (0b100)
#define RCC_CFGR_MCO1_HSI (0b00)
#define RCC_CFGR_MCO1_HSE (0b10)
#define RCC_CFGR_MCO1_PLL (0b11)
#define RCC_CFGR_MCO1_BIT 21
#define RCC_CFGR_MCO1_MASK (0b11)
#define RCC_CFGR_MCO1PRE_DIV4 (0b110)
#define RCC_CFGR_MCO1PRE_BIT 24
#define RCC_CFGR_MCO1PRE_MASK (0b111)
#define RCC_CFGR_PPRE2_BIT 13
#define RCC_CFGR_PPRE2_MASK (0b111)
@@ -2075,6 +2094,7 @@ struct rcc {
#define RCC_CFGR_SWS_MASK (0b11)
#define RCC_CFGR_SW_PLL (0b10)
#define RCC_CFGR_SW_PLL (0b10)
#define RCC_CFGR_SW_BIT 0
@@ -2132,13 +2152,21 @@ struct gpio {
#define GPIOA ((struct gpio *) GPIOA_BASE_ADDR)
#define GPIO_MODER_MODER3_BIT 7
#define GPIO_MODER_AF_MODE (0b10)
#define GPIO_MODER_MODER8_BIT 16
#define GPIO_MODER_MODER8_MASK (0b11)
#define GPIO_MODER_MODER3_BIT 6
#define GPIO_MODER_MODER3_MASK (0b11)
#define GPIO_MODER_MODER3_AF (0b10)
#define GPIO_MODER_MODER2_BIT 4
#define GPIO_MODER_MODER2_MASK (0b11)
#define GPIO_MODER_MODER2_AF (0b10)
#define GPIO_AFRH_AFRH8_BIT 0
#define GPIO_AFRH_AFRH8_MASK (0b1111)
#define GPIO_AFRH_AFRH8_MCO_1 (0b0000)
#define GPIO_AFRL_AFRL3_BIT 12
@@ -2173,9 +2201,9 @@ typedef enum {
void gpio_set_mode(uint16_t pin, GPIO_MODE mode);
void gpio_write(uint16_t pin,
# 64 "src/gpio.h" 3 4
# 72 "src/gpio.h" 3 4
_Bool
# 64 "src/gpio.h"
# 72 "src/gpio.h"
val);
# 3 "src/usart.c" 2
# 1 "src/usart.h" 1
@@ -2250,8 +2278,8 @@ void usart2_init(void) {
((struct gpio *) (0x40020000U))->MODER &= ~((0b11) << 4);
((struct gpio *) (0x40020000U))->MODER |= ((0b10) << 4);
((struct gpio *) (0x40020000U))->MODER &= ~((0b11) << 7);
((struct gpio *) (0x40020000U))->MODER |= ((0b10) << 7);
((struct gpio *) (0x40020000U))->MODER &= ~((0b11) << 6);
((struct gpio *) (0x40020000U))->MODER |= ((0b10) << 6);
((struct gpio *) (0x40020000U))->AFRL &= ~((0b1111) << 8);
@@ -2260,19 +2288,25 @@ void usart2_init(void) {
((struct gpio *) (0x40020000U))->AFRL |= ((0b0111) << 12);
((struct gpio *) (0x40020000U))->MODER &= ~((0b11) << 16);
((struct gpio *) (0x40020000U))->MODER |= ((0b10) << 16);
((struct gpio *) (0x40020000U))->AFRH &= ~((0b1111) << 0);
((struct gpio *) (0x40020000U))->AFRH |= ((0b0000) << 0);
((struct rcc *) (0x40023800U))->APB1ENR |= (1 << 17);
((struct usart *) (0x40004400U))->CR1 = 0;
((struct usart *) (0x40004400U))->CR2 = 0;
((struct usart *) (0x40004400U))->CR3 = 0;
# 54 "src/usart.c"
# 55 "src/usart.c"
((struct usart *) (0x40004400U))->BRR &= ~((0b111111111111) << 4);
((struct usart *) (0x40004400U))->BRR |= (0x34 << 4);
((struct usart *) (0x40004400U))->BRR |= (0x68 << 4);
((struct usart *) (0x40004400U))->BRR &= ~((0b111) << 0);
((struct usart *) (0x40004400U))->BRR |= (0x0 << 0);
((struct usart *) (0x40004400U))->BRR |= (0x2AB << 0);
((struct usart *) (0x40004400U))->CR1 |= (1 << 3);
@@ -2288,8 +2322,8 @@ void usart2_write_byte(uint8_t c) {
((struct usart *) (0x40004400U))->DR = c;
while ((((struct usart *) (0x40004400U))->SR & (1 << 7)) == 0);
while (!(((struct usart *) (0x40004400U))->SR & (1 << 6)));
}
void usart2_write(char *buf) {