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Disable FLASH wait states

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As it blocks the mc from reaching a ready state for unknown reason(s)
This commit is contained in:
Alexander Heldt
2025-01-01 12:40:01 +01:00
parent 1ae81edf57
commit 4600e8e838
7 changed files with 167 additions and 180 deletions
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BIN
build/final.elf
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228
build/final.elf.map
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@@ -157,7 +157,7 @@ LOAD build/usart.o
0x08000000 interrupt_vector_table
0x08000198 . = ALIGN (0x4)
.text 0x08000198 0x53c
.text 0x08000198 0x520
0x08000198 . = ALIGN (0x4)
*(.text)
*(.text.*)
@@ -172,129 +172,129 @@ LOAD build/usart.o
0x08000292 gpio_write
*fill* 0x080002de 0x2
.text.system_clock_init
0x080002e0 0x138 build/main.o
.text.main 0x08000418 0x9c build/main.o
0x08000418 main
0x080002e0 0x11c build/main.o
.text.main 0x080003fc 0x9c build/main.o
0x080003fc main
.text.init_memory
0x080004b4 0x64 build/startup.o
0x080004b4 init_memory
.text.reset 0x08000518 0x10 build/startup.o
0x08000518 reset
0x08000498 0x64 build/startup.o
0x08000498 init_memory
.text.reset 0x080004fc 0x10 build/startup.o
0x080004fc reset
.text.default_handler
0x08000528 0x8 build/startup.o
0x08000528 exti0
0x08000528 debug_monitor
0x08000528 rcc
0x08000528 x
0x08000528 sdio
0x08000528 usage_fault
0x08000528 tim1_up_tim10
0x08000528 usart1
0x08000528 i2c3_er
0x08000528 spi2
0x08000528 dma1_stream1
0x08000528 bus_fault
0x08000528 spi5
0x08000528 exti3
0x08000528 dma2_stream5
0x08000528 tim2
0x08000528 dma1_stream6
0x08000528 default_handler
0x08000528 i2c1_er
0x08000528 hard_fault
0x08000528 usart6
0x08000528 exti15_10
0x08000528 usart2
0x08000528 pend_sv
0x08000528 i2c1_ev
0x08000528 wwdg
0x08000528 adc
0x08000528 rtc_alarm
0x08000528 spi3
0x08000528 exti1
0x08000528 mem_manage
0x08000528 dma2_stream1
0x08000528 dma1_stream2
0x08000528 dma2_stream3
0x08000528 sv_call
0x08000528 tim3
0x08000528 otg_fs
0x08000528 dma1_stream5
0x08000528 dma2_stream6
0x08000528 flash
0x08000528 tamp_stamp
0x08000528 i2c3_ev
0x08000528 rtc_wkup
0x08000528 dma2_stream0
0x08000528 pvd
0x08000528 fpu
0x08000528 exti4
0x08000528 exti2
0x08000528 spi1
0x08000528 dma1_stream0
0x08000528 tim1_brk_tim9
0x08000528 i2c2_ev
0x08000528 otg_fs_wkup
0x08000528 spi4
0x08000528 dma2_stream2
0x08000528 tim1_cc
0x08000528 tim1_trg_com_tim11
0x08000528 exti9_5
0x08000528 dma1_stream3
0x08000528 dma2_stream4
0x08000528 i2c2_er
0x08000528 dma2_stream7
0x08000528 dma1_stream7
0x08000528 nmi
0x08000528 systick
0x08000528 tim4
0x08000528 tim5
0x08000528 dma1_stream4
0x0800050c 0x8 build/startup.o
0x0800050c exti0
0x0800050c debug_monitor
0x0800050c rcc
0x0800050c x
0x0800050c sdio
0x0800050c usage_fault
0x0800050c tim1_up_tim10
0x0800050c usart1
0x0800050c i2c3_er
0x0800050c spi2
0x0800050c dma1_stream1
0x0800050c bus_fault
0x0800050c spi5
0x0800050c exti3
0x0800050c dma2_stream5
0x0800050c tim2
0x0800050c dma1_stream6
0x0800050c default_handler
0x0800050c i2c1_er
0x0800050c hard_fault
0x0800050c usart6
0x0800050c exti15_10
0x0800050c usart2
0x0800050c pend_sv
0x0800050c i2c1_ev
0x0800050c wwdg
0x0800050c adc
0x0800050c rtc_alarm
0x0800050c spi3
0x0800050c exti1
0x0800050c mem_manage
0x0800050c dma2_stream1
0x0800050c dma1_stream2
0x0800050c dma2_stream3
0x0800050c sv_call
0x0800050c tim3
0x0800050c otg_fs
0x0800050c dma1_stream5
0x0800050c dma2_stream6
0x0800050c flash
0x0800050c tamp_stamp
0x0800050c i2c3_ev
0x0800050c rtc_wkup
0x0800050c dma2_stream0
0x0800050c pvd
0x0800050c fpu
0x0800050c exti4
0x0800050c exti2
0x0800050c spi1
0x0800050c dma1_stream0
0x0800050c tim1_brk_tim9
0x0800050c i2c2_ev
0x0800050c otg_fs_wkup
0x0800050c spi4
0x0800050c dma2_stream2
0x0800050c tim1_cc
0x0800050c tim1_trg_com_tim11
0x0800050c exti9_5
0x0800050c dma1_stream3
0x0800050c dma2_stream4
0x0800050c i2c2_er
0x0800050c dma2_stream7
0x0800050c dma1_stream7
0x0800050c nmi
0x0800050c systick
0x0800050c tim4
0x0800050c tim5
0x0800050c dma1_stream4
.text.tim4_init
0x08000530 0x40 build/timer.o
0x08000530 tim4_init
0x08000514 0x40 build/timer.o
0x08000514 tim4_init
.text.tim4_start
0x08000570 0x20 build/timer.o
0x08000570 tim4_start
0x08000554 0x20 build/timer.o
0x08000554 tim4_start
.text.usart2_init
0x08000590 0xb8 build/usart.o
0x08000590 usart2_init
0x08000574 0xb8 build/usart.o
0x08000574 usart2_init
.text.usart2_start
0x08000648 0x20 build/usart.o
0x08000648 usart2_start
0x0800062c 0x20 build/usart.o
0x0800062c usart2_start
.text.usart2_write_byte
0x08000668 0x30 build/usart.o
0x08000668 usart2_write_byte
0x0800064c 0x30 build/usart.o
0x0800064c usart2_write_byte
.text.usart2_write
0x08000698 0x2a build/usart.o
0x08000698 usart2_write
0x0800067c 0x2a build/usart.o
0x0800067c usart2_write
*(.rodata)
*fill* 0x080006c2 0x2
.rodata 0x080006c4 0xf build/main.o
*fill* 0x080006a6 0x2
.rodata 0x080006a8 0xf build/main.o
*(.rodata.*)
0x080006d4 . = ALIGN (0x4)
*fill* 0x080006d3 0x1
0x080006d4 _data_addr = LOADADDR (.data)
0x080006b8 . = ALIGN (0x4)
*fill* 0x080006b7 0x1
0x080006b8 _data_addr = LOADADDR (.data)
.glue_7 0x080006d4 0x0
.glue_7 0x080006d4 0x0 linker stubs
.glue_7 0x080006b8 0x0
.glue_7 0x080006b8 0x0 linker stubs
.glue_7t 0x080006d4 0x0
.glue_7t 0x080006d4 0x0 linker stubs
.glue_7t 0x080006b8 0x0
.glue_7t 0x080006b8 0x0 linker stubs
.vfp11_veneer 0x080006d4 0x0
.vfp11_veneer 0x080006d4 0x0 linker stubs
.vfp11_veneer 0x080006b8 0x0
.vfp11_veneer 0x080006b8 0x0 linker stubs
.v4_bx 0x080006d4 0x0
.v4_bx 0x080006d4 0x0 linker stubs
.v4_bx 0x080006b8 0x0
.v4_bx 0x080006b8 0x0 linker stubs
.iplt 0x080006d4 0x0
.iplt 0x080006d4 0x0 build/main.o
.iplt 0x080006b8 0x0
.iplt 0x080006b8 0x0 build/main.o
.rel.dyn 0x080006d4 0x0
.rel.iplt 0x080006d4 0x0 build/main.o
.rel.dyn 0x080006b8 0x0
.rel.iplt 0x080006b8 0x0 build/main.o
.data 0x20000000 0x0 load address 0x080006d4
.data 0x20000000 0x0 load address 0x080006b8
0x20000000 . = ALIGN (0x4)
0x20000000 _data_start = .
*(.data)
@@ -302,10 +302,10 @@ LOAD build/usart.o
0x20000000 . = ALIGN (0x4)
0x20000000 _data_end = .
.igot.plt 0x20000000 0x0 load address 0x080006d4
.igot.plt 0x20000000 0x0 load address 0x080006b8
.igot.plt 0x20000000 0x0 build/main.o
.bss 0x20000000 0x0 load address 0x080006d4
.bss 0x20000000 0x0 load address 0x080006b8
0x20000000 . = ALIGN (0x4)
0x20000000 _bss_start = .
*(.bss)
@@ -384,12 +384,12 @@ LOAD linker stubs
.debug_macro 0x00003c9f 0xb74 build/usart.o
.debug_macro 0x00004813 0x40 build/usart.o
.debug_line 0x00000000 0x69d
.debug_line 0x00000000 0x691
.debug_line 0x00000000 0x179 build/gpio.o
.debug_line 0x00000179 0x1de build/main.o
.debug_line 0x00000357 0xea build/startup.o
.debug_line 0x00000441 0xdf build/timer.o
.debug_line 0x00000520 0x17d build/usart.o
.debug_line 0x00000179 0x1d2 build/main.o
.debug_line 0x0000034b 0xea build/startup.o
.debug_line 0x00000435 0xdf build/timer.o
.debug_line 0x00000514 0x17d build/usart.o
.debug_str 0x00000000 0x626f
.debug_str 0x00000000 0x53d8 build/gpio.o

97
build/main.S
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@@ -175,42 +175,27 @@ system_clock_init:
.loc 1 62 41
orr r3, r3, #512
str r3, [r2]
.loc 1 65 35
ldr r3, .L5+12
ldr r3, [r3]
ldr r2, .L5+12
.loc 1 65 41
bic r3, r3, #15
str r3, [r2]
.loc 1 66 33
.loc 1 70 33
ldr r3, .L5
ldr r3, [r3, #8]
ldr r2, .L5
.loc 1 66 40
orr r3, r3, #272
orr r3, r3, #1
str r3, [r2, #8]
.loc 1 69 33
ldr r3, .L5
ldr r3, [r3, #8]
ldr r2, .L5
.loc 1 69 40
.loc 1 70 40
orr r3, r3, #2
str r3, [r2, #8]
.loc 1 73 9
.loc 1 74 9
nop
.L4:
.loc 1 73 42 discriminator 1
.loc 1 74 42 discriminator 1
ldr r3, .L5
ldr r3, [r3, #8]
.loc 1 73 49 discriminator 1
.loc 1 74 49 discriminator 1
lsrs r3, r3, #2
.loc 1 73 55 discriminator 1
.loc 1 74 55 discriminator 1
and r3, r3, #3
.loc 1 73 65 discriminator 1
.loc 1 74 65 discriminator 1
cmp r3, #2
bne .L4
.loc 1 74 1
.loc 1 75 1
nop
nop
mov sp, r7
@@ -243,7 +228,7 @@ system_clock_init:
.type main, %function
main:
.LFB1:
.loc 1 76 16
.loc 1 77 16
.cfi_startproc
@ args = 0, pretend = 0, frame = 8
@ frame_needed = 1, uses_anonymous_args = 0
@@ -255,60 +240,60 @@ main:
.cfi_def_cfa_offset 16
add r7, sp, #0
.cfi_def_cfa_register 7
.loc 1 77 3
bl system_clock_init
.loc 1 78 3
bl tim4_init
bl system_clock_init
.loc 1 79 3
bl tim4_init
.loc 1 80 3
bl usart2_init
.loc 1 81 3
bl tim4_start
.loc 1 82 3
bl tim4_start
.loc 1 83 3
bl usart2_start
.loc 1 84 12
.loc 1 85 12
movw r3, #525
strh r3, [r7, #2] @ movhi
.loc 1 85 33
.loc 1 86 33
ldr r3, .L10
ldr r3, [r3, #48]
.loc 1 85 57
.loc 1 86 57
ldrh r2, [r7, #2]
lsrs r2, r2, #8
uxth r2, r2
mov r1, r2
.loc 1 85 49
.loc 1 86 49
movs r2, #1
lsls r2, r2, r1
mov r1, r2
.loc 1 85 33
.loc 1 86 33
ldr r2, .L10
.loc 1 85 43
.loc 1 86 43
orrs r3, r3, r1
str r3, [r2, #48]
.loc 1 86 3
.loc 1 87 3
ldrh r3, [r7, #2]
movs r1, #1
mov r0, r3
bl gpio_set_mode
.loc 1 88 54
.loc 1 89 54
ldr r3, .L10+4
ldr r3, [r3, #36]
.loc 1 88 12
.loc 1 89 12
strh r3, [r7, #6] @ movhi
.loc 1 89 7
.loc 1 90 7
movs r3, #0
strb r3, [r7, #5]
.L9:
.loc 1 91 39
.loc 1 92 39
ldr r3, .L10+4
ldr r2, [r3, #36]
.loc 1 91 45
.loc 1 92 45
ldrh r3, [r7, #6]
subs r3, r2, r3
.loc 1 91 5
.loc 1 92 5
cmp r3, #249
bls .L9
.loc 1 92 3
.loc 1 93 3
ldrb r3, [r7, #5] @ zero_extendqisi2
cmp r3, #0
ite ne
@@ -317,26 +302,26 @@ main:
uxtb r3, r3
eor r3, r3, #1
uxtb r3, r3
.loc 1 92 10
.loc 1 93 10
strb r3, [r7, #5]
ldrb r3, [r7, #5]
and r3, r3, #1
strb r3, [r7, #5]
.loc 1 93 3
.loc 1 94 3
ldrb r2, [r7, #5] @ zero_extendqisi2
ldrh r3, [r7, #2]
mov r1, r2
mov r0, r3
bl gpio_write
.loc 1 95 3
.loc 1 96 3
ldr r0, .L10+8
bl usart2_write
.loc 1 97 45
.loc 1 98 45
ldr r3, .L10+4
ldr r3, [r3, #36]
.loc 1 97 11
.loc 1 98 11
strh r3, [r7, #6] @ movhi
.loc 1 91 5
.loc 1 92 5
b .L9
.L11:
.align 2
@@ -893,7 +878,7 @@ main:
.uleb128 0x13
.4byte .LASF1036
.byte 0x1
.byte 0x4c
.byte 0x4d
.byte 0x5
.4byte 0x7a
.4byte .LFB1
@@ -904,7 +889,7 @@ main:
.uleb128 0x14
.ascii "led\000"
.byte 0x1
.byte 0x54
.byte 0x55
.byte 0xc
.4byte 0x88
.uleb128 0x2
@@ -912,7 +897,7 @@ main:
.sleb128 -14
.uleb128 0xc
.4byte .LASF1031
.byte 0x58
.byte 0x59
.byte 0xc
.4byte 0x88
.uleb128 0x2
@@ -920,7 +905,7 @@ main:
.sleb128 -10
.uleb128 0xc
.4byte .LASF1032
.byte 0x59
.byte 0x5a
.byte 0x7
.4byte 0x3ec
.uleb128 0x2
@@ -4321,7 +4306,7 @@ main:
.uleb128 0x24
.4byte .LASF924
.byte 0
.section .debug_macro,"G",%progbits,wm4.flash.h.2.51d6f0499046dca8c8d7cee08875e55f,comdat
.section .debug_macro,"G",%progbits,wm4.flash.h.2.f966f6c905ff507203ee6a1fd62d64ef,comdat
.Ldebug_macro17:
.2byte 0x5
.byte 0
@@ -5138,8 +5123,6 @@ main:
.ascii "_END_STD_C \000"
.LASF852:
.ascii "true ((_Bool)+1u)\000"
.LASF932:
.ascii "FLASH_ACR_LATENCY_3_WAIT_STATES (0x0111)\000"
.LASF599:
.ascii "UINT_LEAST16_MAX (__UINT_LEAST16_MAX__)\000"
.LASF123:
@@ -6550,6 +6533,8 @@ main:
.ascii "__ARM_FEATURE_CDE_COPROC\000"
.LASF765:
.ascii "PRIoLEAST32 __PRI32LEAST(o)\000"
.LASF932:
.ascii "FLASH_ACR_LATENCY_3_WAIT_STATES (0b0011)\000"
.LASF91:
.ascii "__INTMAX_C(c) c ## LL\000"
.ident "GCC: (Arm GNU Toolchain 12.3.Rel1 (Build arm-12.35)) 12.3.1 20230626"

15
build/main.i
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@@ -2200,7 +2200,7 @@ struct flash {
#define FLASH_ACR_ICEN_ENABLE (1 <<FLASH_ACR_ICEN_BIT)
#define FLASH_ACR_LATENCY_3_WAIT_STATES (0x0111)
#define FLASH_ACR_LATENCY_3_WAIT_STATES (0b0011)
#define FLASH_ACR_LATENCY_BIT 0
#define FLASH_ACR_LATENCY_MASK (0b1111)
@@ -2371,8 +2371,9 @@ static void system_clock_init(void) {
((struct flash *) (0x40023C00U))->ACR |= (1 <<9);
((struct flash *) (0x40023C00U))->ACR &= ~((0b1111) << 0);
((struct rcc *) (0x40023800U))->CFGR |= ((0x0111) << 0);
((struct rcc *) (0x40023800U))->CFGR |= (((0b10) & (0b11)) << 0);
@@ -2396,13 +2397,13 @@ int main(void) {
uint16_t counter = ((struct timer *) (0x40000800U))->CNT;
# 89 "src/main.c" 3 4
# 90 "src/main.c" 3 4
_Bool
# 89 "src/main.c"
# 90 "src/main.c"
led_on =
# 89 "src/main.c" 3 4
# 90 "src/main.c" 3 4
((_Bool)+0u)
# 89 "src/main.c"
# 90 "src/main.c"
;
while(1) {
if ((((struct timer *) (0x40000800U))->CNT - counter) >= 250) {

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build/main.o
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2
src/flash.h
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@@ -25,7 +25,7 @@ struct flash {
#define FLASH_ACR_ICEN_ENABLE (1 <<FLASH_ACR_ICEN_BIT)
// Latency
#define FLASH_ACR_LATENCY_3_WAIT_STATES (0x0111)
#define FLASH_ACR_LATENCY_3_WAIT_STATES (0b0011)
#define FLASH_ACR_LATENCY_BIT 0 // Bits [3:0]
#define FLASH_ACR_LATENCY_MASK (0b1111)

5
src/main.c
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@@ -61,9 +61,10 @@ static void system_clock_init(void) {
FLASH->ACR |= FLASH_ACR_DCEN_ENABLE;
FLASH->ACR |= FLASH_ACR_ICEN_ENABLE;
// TODO breaks with these flash settings on; turning off for now
// Set latency to be 3 wait states (TODO: understand why exactly 3)
FLASH->ACR &= ~(FLASH_ACR_LATENCY_MASK << FLASH_ACR_LATENCY_BIT);
RCC->CFGR |= (FLASH_ACR_LATENCY_3_WAIT_STATES << FLASH_ACR_LATENCY_BIT);
/* FLASH->ACR &= ~(FLASH_ACR_LATENCY_MASK << FLASH_ACR_LATENCY_BIT); */
/* RCC->CFGR |= (FLASH_ACR_LATENCY_3_WAIT_STATES << FLASH_ACR_LATENCY_BIT); */
// Use PLL as system clock
RCC->CFGR |= RCC_CFGR_SW(RCC_CFGR_SW_PLL);