alex/stm32-falling-sand
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wip working usart, not receiving over tty

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This commit is contained in:
Alexander Heldt
2024-12-26 15:02:52 +01:00
parent a3c1de878a
commit 592717d900
27 changed files with 10185 additions and 944 deletions
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14
build/timer.i
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@@ -1,5 +1,5 @@
# 0 "src/timer.c"
# 1 "/home/alex/code/own/c-compile-experiments//"
# 1 "/home/alex/code/own/stm32-falling-sand//"
# 0 "<built-in>"
#define __STDC__ 1
# 0 "<built-in>"
@@ -2082,9 +2082,17 @@ struct rcc {
#define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT)
#define RCC_AHB1ENR_GPIOAEN_BIT 0
#define RCC_AHB1ENR_GPIOAEN_ENABLE (1 << RCC_AHB1ENR_GPIOAEN_BIT)
#define RCC_APB1ENR_PWREN_BIT 28
#define RCC_APB1ENR_PWREN_CLOCK_ENABLE (1 << RCC_APB1ENR_PWREN_BIT)
#define RCC_APB1ENR_USART2EN_BIT 17
#define RCC_APB1ENR_USART2EN_ENABLE (1 << RCC_APB1ENR_USART2EN_BIT)
#define RCC_APB1ENR_TIM4_BIT 2
#define RCC_APB1ENR_TIM4_ENABLE (1 << RCC_APB1ENR_TIM4_BIT)
# 2 "src/timer.c" 2
@@ -2120,8 +2128,8 @@ struct timer {
#define TIM4_BASE_ADDR (0x40000800U)
#define TIM4 ((struct timer *) TIM4_BASE_ADDR)
#define TIM4_CR_CEN_BIT 0
#define TIM4_ENABLE (1 << TIM4_CR_CEN_BIT)
#define TIM_CR1_CEN_BIT 0
#define TIM_ENABLE (1 << TIM_CR1_CEN_BIT)
void tim4_init(void);
void tim4_start(void);