From 6f6caa29cac695f3489dad55a80d8041e1589181 Mon Sep 17 00:00:00 2001
From: Alexander Heldt <me@alexanderheldt.se>
Date: Wed, 1 Jan 2025 12:37:52 +0100
Subject: [PATCH] Add ability to debug clock with MCO1

---
 src/gpio.h  |  1 +
 src/rcc.h   | 13 +++++++++++++
 src/usart.c |  9 +++++++++
 3 files changed, 23 insertions(+)

diff --git a/src/gpio.h b/src/gpio.h
index 5b6e159..8aa8c07 100644
--- a/src/gpio.h
+++ b/src/gpio.h
@@ -18,6 +18,7 @@ struct gpio {
 };
 
 // AFRH, AFRL registers
+#define GPIO_AF_MCO_1 (0b0000)     // Alternative function 0 (AF0)
 #define GPIO_AF_USART2_RX (0b0111) // Alternative function 7 (AF7)
 #define GPIO_AF_USART2_TX (0b0111) // Alternative function 7 (AF7)
 
diff --git a/src/rcc.h b/src/rcc.h
index d898f6b..6f2a831 100644
--- a/src/rcc.h
+++ b/src/rcc.h
@@ -87,6 +87,19 @@ struct rcc {
 #define RCC_CFGR_PPRE_DIV_NONE	0
 #define RCC_CFGR_PPRE_DIV_2	(0b100)
 
+// Microcontroller clock output 1
+#define RCC_CFGR_MCO1_HSE (0b10)
+#define RCC_CFGR_MCO1_PLL (0b11)
+
+#define RCC_CFGR_MCO1_BIT 21 // Bits [22:21]
+#define RCC_CFGR_MCO1_MASK (0b11)
+
+#define RCC_CFGR_MCO1PRE_DIV4 (0b110)
+#define RCC_CFGR_MCO1PRE_DIV2 (0b100)
+
+#define RCC_CFGR_MCO1PRE_BIT 24 // Bits [26:24]
+#define RCC_CFGR_MCO1PRE_MASK (0b111)
+
 // APB2
 #define RCC_CFGR_PPRE2_BIT 13 // Bits [15:13]
 #define RCC_CFGR_PPRE2_MASK (0b111)
diff --git a/src/usart.c b/src/usart.c
index e90bdaa..9c2a8b0 100644
--- a/src/usart.c
+++ b/src/usart.c
@@ -15,6 +15,15 @@ void usart2_init(void) {
   gpio_set_mode(rxPin, GPIO_MODE_AF);
   gpio_set_af(rxPin, GPIO_AF_USART2_RX);
 
+  // Enable MC01; for debugging
+  /* uint16_t clockOutPin = PIN('A', 8); */
+  /* gpio_set_mode(clockOutPin, GPIO_MODE_AF); */
+  /* gpio_set_af(clockOutPin, GPIO_AF_MCO_1); */
+  /* RCC->CFGR &= ~(RCC_CFGR_MCO1_MASK << RCC_CFGR_MCO1_BIT); */
+  /* RCC->CFGR |= (RCC_CFGR_MCO1_HSE << RCC_CFGR_MCO1_BIT); */
+  /* RCC->CFGR |= (RCC_CFGR_MCO1_PLL << RCC_CFGR_MCO1_BIT); */
+  /* RCC->CFGR &= ~(RCC_CFGR_MCO1PRE_MASK << RCC_CFGR_MCO1PRE_BIT); */
+  /* RCC->CFGR |= (RCC_CFGR_MCO1PRE_DIV4 << RCC_CFGR_MCO1PRE_BIT); */
 
   // Enable USART
   RCC->APB1ENR |= RCC_APB1ENR_USART2EN_ENABLE;