From 916d7d9620a7f87a5c262ab7057bd0a611eb7e51 Mon Sep 17 00:00:00 2001
From: Alexander Heldt <me@alexanderheldt.se>
Date: Mon, 30 Dec 2024 11:47:18 +0100
Subject: [PATCH] Set correct PLL N for 96MHz

---
 build/final.elf | Bin 55108 -> 55108 bytes
 build/main.S    |   2 +-
 build/main.i    |   2 +-
 build/main.o    | Bin 48592 -> 48592 bytes
 src/main.c      |   2 +-
 5 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/build/final.elf b/build/final.elf
index 5f46cac09cd12977bdc5da13aab988698f597673..cdc8fff42d932b1491b296d84c5c233e0e2b8b06 100755
GIT binary patch
delta 16
YcmX@Ij`_$s<_)dFj0T(Ag!df=06s(qF#rGn

delta 16
YcmX@Ij`_$s<_)dFjE0-rg!df=06t0wG5`Po

diff --git a/build/main.S b/build/main.S
index 2f2ba27..de60756 100644
--- a/build/main.S
+++ b/build/main.S
@@ -231,7 +231,7 @@ system_clock_init:
 .L5:
 	.word	1073887232
 	.word	1073770496
-	.word	67252505
+	.word	67252249
 	.word	1073888256
 	.cfi_endproc
 .LFE0:
diff --git a/build/main.i b/build/main.i
index 5757b32..1cc263b 100644
--- a/build/main.i
+++ b/build/main.i
@@ -2269,7 +2269,7 @@ static void system_clock_init(void) {
   ((struct rcc *) (0x40023800U))->PLLCFGR |= (1 << 22);
 
 
-  ((struct rcc *) (0x40023800U))->PLLCFGR |= ((25 & (0b111111)) << 0) | ((196 & (0b111111111)) << 6) | ((2 & (0b11)) << 16) | ((4 & (0b1111)) << 24);
+  ((struct rcc *) (0x40023800U))->PLLCFGR |= ((25 & (0b111111)) << 0) | ((192 & (0b111111111)) << 6) | ((2 & (0b11)) << 16) | ((4 & (0b1111)) << 24);
 
 
   ((struct rcc *) (0x40023800U))->CFGR &= ~((0b1111) << 4);
diff --git a/build/main.o b/build/main.o
index 7b6ef1767ddea45b911ae85cf27403458f72408b..35ff02f8bf973aef55120b2870ca52db8dd4a4e2 100644
GIT binary patch
delta 16
Ycmccco9V)DrVXA<j0T&%nA&y&07GX72LJ#7

delta 16
Ycmccco9V)DrVXA<jE0-NnA&y&07GpD2mk;8

diff --git a/src/main.c b/src/main.c
index 230a8e5..26025cc 100644
--- a/src/main.c
+++ b/src/main.c
@@ -32,7 +32,7 @@ static void system_clock_init(void) {
   RCC->PLLCFGR |= RCC_PLLCFGR_PLLSRC_HSE;
 
   // Settings to achieve system clock of 96Mhz
-  RCC->PLLCFGR |= RCC_PLLCFGR_PLLM(25) | RCC_PLLCFGR_PLLN(196) | RCC_PLLCFGR_PLLP(2) | RCC_PLLCFGR_PLLQ(4);
+  RCC->PLLCFGR |= RCC_PLLCFGR_PLLM(25) | RCC_PLLCFGR_PLLN(192) | RCC_PLLCFGR_PLLP(2) | RCC_PLLCFGR_PLLQ(4);
 
   // Set AHB prescalar to /1
   RCC->CFGR &= ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_BIT);