wip

2024-12-30 16:58:26 +01:00
parent 9e4aaeabd5
commit 953cc58655
26 changed files with 10968 additions and 1361 deletions
@@ -1,5 +1,5 @@
 # 0 "src/main.c"
-# 1 "/home/alex/code/own/c-compile-experiments//"
+# 1 "/home/alex/code/own/stm32-falling-sand//"
 # 0 "<built-in>"
 #define __STDC__ 1
 # 0 "<built-in>"
@@ -2029,6 +2029,11 @@ struct rcc {
 #define RCC_CR_PLLON_ON (1 << RCC_CR_PLLON_BIT)


+#define RCC_CR_CSS_BIT 19
+#define RCC_CR_CSS_ON (1 << RCC_CR_CSS_BIT)
+
+
+
 #define RCC_CR_HSERDY_BIT 17
 #define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT)

@@ -2051,6 +2056,7 @@ struct rcc {

 #define RCC_PLLCFGR_PLLSRC_BIT 22
 #define RCC_PLLCFGR_PLLSRC_HSE (1 << RCC_PLLCFGR_PLLSRC_BIT)
+#define RCC_PLLCFGR_PLLSRC_HSI (0 << RCC_PLLCFGR_PLLSRC_BIT)

 #define RCC_PLLCFGR_PLLP_BIT 16
 #define RCC_PLLCFGR_PLLP_MASK (0b11)
@@ -2070,6 +2076,21 @@ struct rcc {
 #define RCC_CFGR_PPRE_DIV_2 (0b100)


+#define RCC_CFGR_MCO1_HSI (0b00)
+#define RCC_CFGR_MCO1_HSE (0b10)
+#define RCC_CFGR_MCO1_PLL (0b11)
+
+#define RCC_CFGR_MCO1_BIT 21
+#define RCC_CFGR_MCO1_MASK (0b11)
+
+#define RCC_CFGR_MCO1PRE_DIV5 (0b111)
+#define RCC_CFGR_MCO1PRE_DIV4 (0b110)
+#define RCC_CFGR_MCO1PRE_DIV2 (0b100)
+
+#define RCC_CFGR_MCO1PRE_BIT 24
+#define RCC_CFGR_MCO1PRE_MASK (0b111)
+
+
 #define RCC_CFGR_PPRE2_BIT 13
 #define RCC_CFGR_PPRE2_MASK (0b111)

@@ -2097,9 +2118,17 @@ struct rcc {
 #define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT)


+
+#define RCC_AHB1ENR_GPIOAEN_BIT 0
+#define RCC_AHB1ENR_GPIOAEN_ENABLE (1 << RCC_AHB1ENR_GPIOAEN_BIT)
+
+
 #define RCC_APB1ENR_PWREN_BIT 28
 #define RCC_APB1ENR_PWREN_CLOCK_ENABLE (1 << RCC_APB1ENR_PWREN_BIT)

+#define RCC_APB1ENR_USART2EN_BIT 17
+#define RCC_APB1ENR_USART2EN_ENABLE (1 << RCC_APB1ENR_USART2EN_BIT)
+
 #define RCC_APB1ENR_TIM4_BIT 2
 #define RCC_APB1ENR_TIM4_ENABLE (1 << RCC_APB1ENR_TIM4_BIT)
 # 5 "src/main.c" 2
@@ -2119,17 +2148,23 @@ struct gpio {
  volatile uint32_t ODR;
  volatile uint32_t BSRR;
  volatile uint32_t LCKR;
-  volatile uint32_t AFRL[2];
-  volatile uint32_t AFRH[2];
+  volatile uint32_t AFRL;
+  volatile uint32_t AFRH;
 };

+
+#define GPIO_AF_MCO_1 (0b0000)
+#define GPIO_AF_USART2_RX (0b0111)
+#define GPIO_AF_USART2_TX (0b0111)
+
 #define GPIO_BASE_ADDR (0x40020000U)
 #define GPIO_PORT_OFFSET (0x400U)
 #define GPIO(port) ((struct gpio*)(uintptr_t)(GPIO_BASE_ADDR + (GPIO_PORT_OFFSET * port)))

-#define BIT(x) (1 << x)

-#define PIN(port,num) ((((port) - 'A') << 8) | num)
+#define PORT(port) (((port) - 'A') << 8)
+
+#define PIN(port,num) (PORT(port) | num)

 #define PINNUM(pin) (pin & 0b1111)

@@ -2143,10 +2178,11 @@ typedef enum {
 } GPIO_MODE;

 void gpio_set_mode(uint16_t pin, GPIO_MODE mode);
+void gpio_set_af(uint16_t pin, uint8_t af);
 void gpio_write(uint16_t pin, 
-# 40 "src/gpio.h" 3 4
+# 47 "src/gpio.h" 3 4
                             _Bool 
-# 40 "src/gpio.h"
+# 47 "src/gpio.h"
                                  val);
 # 6 "src/main.c" 2
 # 1 "src/flash.h" 1
@@ -2177,7 +2213,7 @@ struct flash {
 #define FLASH_ACR_ICEN_ENABLE (1 <<FLASH_ACR_ICEN_BIT)


-#define FLASH_ACR_LATENCY_3_WAIT_STATES (0x0111)
+#define FLASH_ACR_LATENCY_3_WAIT_STATES (0b0011)

 #define FLASH_ACR_LATENCY_BIT 0
 #define FLASH_ACR_LATENCY_MASK (0b1111)
@@ -2237,12 +2273,71 @@ struct timer {
 #define TIM4_BASE_ADDR (0x40000800U)
 #define TIM4 ((struct timer *) TIM4_BASE_ADDR)

-#define TIM4_CR_CEN_BIT 0
-#define TIM4_ENABLE (1 << TIM4_CR_CEN_BIT)
+#define TIM_CR1_CEN_BIT 0
+#define TIM_ENABLE (1 << TIM_CR1_CEN_BIT)

 void tim4_init(void);
 void tim4_start(void);
 # 9 "src/main.c" 2
+# 1 "src/usart.h" 1
+
+#define USART_H_ 
+
+
+
+struct usart {
+  volatile uint32_t SR;
+  volatile uint32_t DR;
+  volatile uint32_t BRR;
+  volatile uint32_t CR1;
+  volatile uint32_t CR2;
+  volatile uint32_t CR3;
+  volatile uint32_t GTPR;
+};
+
+#define USART2_BASE_ADDR (0x40004400U)
+#define USART2 ((struct usart *) USART2_BASE_ADDR)
+
+
+
+#define USART_SR_TXE_BIT 7
+#define USART_SR_TXE_TRANSMITTED (1 << USART_SR_TXE_BIT)
+
+
+#define USART_SR_TC_BIT 6
+#define USART_SR_TC_COMPLETED (1 << USART_SR_TC_BIT)
+
+
+
+#define USART_SR_RXNE_BIT 5
+#define USART_SR_RXNE_READY (1 <<USART_SR_RXNE_BIT)
+
+
+
+#define USART_CR1_UE_BIT 13
+#define USART_CR1_UE_ENABLE (1 << USART_CR1_UE_BIT)
+
+
+#define USART_CR1_TE_BIT 3
+#define USART_CR1_TE_ENABLE (1 << USART_CR1_TE_BIT)
+
+
+#define USART_CR1_RE_BIT 2
+#define USART_CR1_RE_ENABLE (1 << USART_CR1_RE_BIT)
+
+
+#define USART_BRR_MANTISSA_BIT 4
+#define USART_BRR_MANTISSA_MASK (0b111111111111)
+
+#define USART_BRR_FRACTION_BIT 0
+#define USART_BRR_FRACTION_MASK (0b111)
+
+void usart2_init(void);
+void usart2_start(void);
+
+void usart2_write_byte(uint8_t byte);
+void usart2_write(char *buf);
+# 10 "src/main.c" 2

 #define exit 42

@@ -2255,9 +2350,14 @@ static void system_clock_init(void) {
  ((struct pwr *) (0x40007000U))->CR |= ((0b11) << 14);


+  ((struct rcc *) (0x40023800U))->CR &= ~(1 << 0);
+# 34 "src/main.c"
  ((struct rcc *) (0x40023800U))->CR |= (1 << 16);


+  ((struct rcc *) (0x40023800U))->CR |= (1 << 19);
+
+

  while (!(((struct rcc *) (0x40023800U))->CR & (1 << 17)));

@@ -2269,7 +2369,7 @@ static void system_clock_init(void) {
  ((struct rcc *) (0x40023800U))->PLLCFGR |= (1 << 22);


-  ((struct rcc *) (0x40023800U))->PLLCFGR |= ((25 & (0b111111)) << 0) | ((196 & (0b111111111)) << 6) | ((2 & (0b11)) << 16) | ((4 & (0b1111)) << 24);
+  ((struct rcc *) (0x40023800U))->PLLCFGR |= ((25 & (0b111111)) << 0) | ((192 & (0b111111111)) << 6) | ((2 & (0b11)) << 16) | ((4 & (0b1111)) << 24);


  ((struct rcc *) (0x40023800U))->CFGR &= ~((0b1111) << 4);
@@ -2288,33 +2388,32 @@ static void system_clock_init(void) {



-  while (!(((struct rcc *) (0x40023800U))->CR & (1 << 17)));
+  while (!(((struct rcc *) (0x40023800U))->CR & (1 << 25)));


  ((struct flash *) (0x40023C00U))->ACR |= (1 <<10);
  ((struct flash *) (0x40023C00U))->ACR |= (1 <<9);


-  ((struct flash *) (0x40023C00U))->ACR &= ~((0b1111) << 0);
-  ((struct rcc *) (0x40023800U))->CFGR |= ((0x0111) << 0);


-  ((struct rcc *) (0x40023800U))->CFGR &= ~((0b11) << 0);
-  ((struct rcc *) (0x40023800U))->CFGR |= ((0b10) << 0);
+
+
+
+  ((struct rcc *) (0x40023800U))->CFGR |= (((0b10) & (0b11)) << 0);



  while (((((struct rcc *) (0x40023800U))->CFGR >> 2) & (0b11)) != (0b10));
-
-
-  ((struct rcc *) (0x40023800U))->CR &= ~(1 << 0);
 }

 int main(void) {
  (void) system_clock_init();
  (void) tim4_init();
+  (void) usart2_init();

  (void) tim4_start();
+  (void) usart2_start();

  uint16_t led = (((('C') - 'A') << 8) | 13);
  ((struct rcc *) (0x40023800U))->AHB1ENR |= (1 << (led >> 8));
@@ -2322,19 +2421,21 @@ int main(void) {

  uint16_t counter = ((struct timer *) (0x40000800U))->CNT;
  
-# 87 "src/main.c" 3 4
+# 102 "src/main.c" 3 4
 _Bool 
-# 87 "src/main.c"
+# 102 "src/main.c"
      led_on = 
-# 87 "src/main.c" 3 4
+# 102 "src/main.c" 3 4
               ((_Bool)+0u)
-# 87 "src/main.c"
+# 102 "src/main.c"
                    ;
  while(1) {
 if ((((struct timer *) (0x40000800U))->CNT - counter) >= 250) {
  led_on = !led_on;
  gpio_write(led, led_on);

+  usart2_write("hello, world!\n");
+
  counter = ((struct timer *) (0x40000800U))->CNT;
 }
  };