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This commit is contained in:
Alexander Heldt
2024-12-30 16:58:26 +01:00
parent 9e4aaeabd5
commit 953cc58655
26 changed files with 10968 additions and 1361 deletions
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README.md
+35
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@@ -0,0 +1,35 @@
# Falling sand on the STM32F411CE
## Building
Run
```sh
make build
```
## Probe for the board
Run
```sh
st-info --probe
```
## Flashing
Run
```sh
make flash
```
## Debugging
### `st-info --probe` shows 0KB flash
```
> sudo st-info --probe
Found 1 stlink programmers
version: V2J43S28
serial: 0671FF343056363043090732
flash: 0 (pagesize: 16384) <--- 0KB flash
sram: 131072
chipid: 0x431
dev-type: STM32F411xC_xE
```
This can happen when the flash is locked. One way to unlock it is to erase the entire chip via the
Windows application `ST-Link Util`.
build/final.elf
BIN
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Binary file not shown.
build/final.elf.map
+235 -162
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@@ -36,6 +36,7 @@ Discarded input sections
.group 0x00000000 0xc build/main.o .group 0x00000000 0xc build/main.o
.group 0x00000000 0xc build/main.o .group 0x00000000 0xc build/main.o
.group 0x00000000 0xc build/main.o .group 0x00000000 0xc build/main.o
.group 0x00000000 0xc build/main.o
.text 0x00000000 0x0 build/main.o .text 0x00000000 0x0 build/main.o
.data 0x00000000 0x0 build/main.o .data 0x00000000 0x0 build/main.o
.bss 0x00000000 0x0 build/main.o .bss 0x00000000 0x0 build/main.o
@@ -52,7 +53,7 @@ Discarded input sections
.debug_macro 0x00000000 0x89 build/main.o .debug_macro 0x00000000 0x89 build/main.o
.debug_macro 0x00000000 0x4cc build/main.o .debug_macro 0x00000000 0x4cc build/main.o
.debug_macro 0x00000000 0x22 build/main.o .debug_macro 0x00000000 0x22 build/main.o
.debug_macro 0x00000000 0x34 build/main.o .debug_macro 0x00000000 0x46 build/main.o
.group 0x00000000 0xc build/startup.o .group 0x00000000 0xc build/startup.o
.group 0x00000000 0xc build/startup.o .group 0x00000000 0xc build/startup.o
.group 0x00000000 0xc build/startup.o .group 0x00000000 0xc build/startup.o
@@ -96,6 +97,40 @@ Discarded input sections
.debug_macro 0x00000000 0x89 build/timer.o .debug_macro 0x00000000 0x89 build/timer.o
.debug_macro 0x00000000 0x4cc build/timer.o .debug_macro 0x00000000 0x4cc build/timer.o
.debug_macro 0x00000000 0x22 build/timer.o .debug_macro 0x00000000 0x22 build/timer.o
.group 0x00000000 0xc build/usart.o
.group 0x00000000 0xc build/usart.o
.group 0x00000000 0xc build/usart.o
.group 0x00000000 0xc build/usart.o
.group 0x00000000 0xc build/usart.o
.group 0x00000000 0xc build/usart.o
.group 0x00000000 0xc build/usart.o
.group 0x00000000 0xc build/usart.o
.group 0x00000000 0xc build/usart.o
.group 0x00000000 0xc build/usart.o
.group 0x00000000 0xc build/usart.o
.group 0x00000000 0xc build/usart.o
.group 0x00000000 0xc build/usart.o
.group 0x00000000 0xc build/usart.o
.group 0x00000000 0xc build/usart.o
.group 0x00000000 0xc build/usart.o
.text 0x00000000 0x0 build/usart.o
.data 0x00000000 0x0 build/usart.o
.bss 0x00000000 0x0 build/usart.o
.debug_macro 0x00000000 0x22 build/usart.o
.debug_macro 0x00000000 0x75 build/usart.o
.debug_macro 0x00000000 0x2a build/usart.o
.debug_macro 0x00000000 0x5c build/usart.o
.debug_macro 0x00000000 0x3c build/usart.o
.debug_macro 0x00000000 0x103 build/usart.o
.debug_macro 0x00000000 0x3a build/usart.o
.debug_macro 0x00000000 0x57 build/usart.o
.debug_macro 0x00000000 0x6a build/usart.o
.debug_macro 0x00000000 0x1df build/usart.o
.debug_macro 0x00000000 0x89 build/usart.o
.debug_macro 0x00000000 0x4cc build/usart.o
.debug_macro 0x00000000 0x198 build/usart.o
.debug_macro 0x00000000 0x22 build/usart.o
.debug_macro 0x00000000 0x76 build/usart.o
Memory Configuration Memory Configuration
@@ -112,6 +147,7 @@ LOAD build/gpio.o
LOAD build/main.o LOAD build/main.o
LOAD build/startup.o LOAD build/startup.o
LOAD build/timer.o LOAD build/timer.o
LOAD build/usart.o
0x20020000 stack_start = (ORIGIN (sram) + LENGTH (sram)) 0x20020000 stack_start = (ORIGIN (sram) + LENGTH (sram))
.isr_vector 0x08000000 0x198 .isr_vector 0x08000000 0x198
@@ -121,126 +157,144 @@ LOAD build/timer.o
0x08000000 interrupt_vector_table 0x08000000 interrupt_vector_table
0x08000198 . = ALIGN (0x4) 0x08000198 . = ALIGN (0x4)
.text 0x08000198 0x358 .text 0x08000198 0x574
0x08000198 . = ALIGN (0x4) 0x08000198 . = ALIGN (0x4)
*(.text) *(.text)
*(.text.*) *(.text.*)
.text.gpio_set_mode .text.gpio_set_mode
0x08000198 0x62 build/gpio.o 0x08000198 0x62 build/gpio.o
0x08000198 gpio_set_mode 0x08000198 gpio_set_mode
.text.gpio_set_af
0x080001fa 0x98 build/gpio.o
0x080001fa gpio_set_af
.text.gpio_write .text.gpio_write
0x080001fa 0x4c build/gpio.o 0x08000292 0x4c build/gpio.o
0x080001fa gpio_write 0x08000292 gpio_write
*fill* 0x08000246 0x2 *fill* 0x080002de 0x2
.text.system_clock_init .text.system_clock_init
0x08000248 0x144 build/main.o 0x080002e0 0x128 build/main.o
.text.main 0x0800038c 0x88 build/main.o .text.main 0x08000408 0x9c build/main.o
0x0800038c main 0x08000408 main
.text.init_memory .text.init_memory
0x08000414 0x64 build/startup.o 0x080004a4 0x64 build/startup.o
0x08000414 init_memory 0x080004a4 init_memory
.text.reset 0x08000478 0x10 build/startup.o .text.reset 0x08000508 0x10 build/startup.o
0x08000478 reset 0x08000508 reset
.text.default_handler .text.default_handler
0x08000488 0x8 build/startup.o 0x08000518 0x8 build/startup.o
0x08000488 exti0 0x08000518 exti0
0x08000488 debug_monitor 0x08000518 debug_monitor
0x08000488 rcc 0x08000518 rcc
0x08000488 x 0x08000518 x
0x08000488 sdio 0x08000518 sdio
0x08000488 usage_fault 0x08000518 usage_fault
0x08000488 tim1_up_tim10 0x08000518 tim1_up_tim10
0x08000488 usart1 0x08000518 usart1
0x08000488 i2c3_er 0x08000518 i2c3_er
0x08000488 spi2 0x08000518 spi2
0x08000488 dma1_stream1 0x08000518 dma1_stream1
0x08000488 bus_fault 0x08000518 bus_fault
0x08000488 spi5 0x08000518 spi5
0x08000488 exti3 0x08000518 exti3
0x08000488 dma2_stream5 0x08000518 dma2_stream5
0x08000488 tim2 0x08000518 tim2
0x08000488 dma1_stream6 0x08000518 dma1_stream6
0x08000488 default_handler 0x08000518 default_handler
0x08000488 i2c1_er 0x08000518 i2c1_er
0x08000488 hard_fault 0x08000518 hard_fault
0x08000488 usart6 0x08000518 usart6
0x08000488 exti15_10 0x08000518 exti15_10
0x08000488 usart2 0x08000518 usart2
0x08000488 pend_sv 0x08000518 pend_sv
0x08000488 i2c1_ev 0x08000518 i2c1_ev
0x08000488 wwdg 0x08000518 wwdg
0x08000488 adc 0x08000518 adc
0x08000488 rtc_alarm 0x08000518 rtc_alarm
0x08000488 spi3 0x08000518 spi3
0x08000488 exti1 0x08000518 exti1
0x08000488 mem_manage 0x08000518 mem_manage
0x08000488 dma2_stream1 0x08000518 dma2_stream1
0x08000488 dma1_stream2 0x08000518 dma1_stream2
0x08000488 dma2_stream3 0x08000518 dma2_stream3
0x08000488 sv_call 0x08000518 sv_call
0x08000488 tim3 0x08000518 tim3
0x08000488 otg_fs 0x08000518 otg_fs
0x08000488 dma1_stream5 0x08000518 dma1_stream5
0x08000488 dma2_stream6 0x08000518 dma2_stream6
0x08000488 flash 0x08000518 flash
0x08000488 tamp_stamp 0x08000518 tamp_stamp
0x08000488 i2c3_ev 0x08000518 i2c3_ev
0x08000488 rtc_wkup 0x08000518 rtc_wkup
0x08000488 dma2_stream0 0x08000518 dma2_stream0
0x08000488 pvd 0x08000518 pvd
0x08000488 fpu 0x08000518 fpu
0x08000488 exti4 0x08000518 exti4
0x08000488 exti2 0x08000518 exti2
0x08000488 spi1 0x08000518 spi1
0x08000488 dma1_stream0 0x08000518 dma1_stream0
0x08000488 tim1_brk_tim9 0x08000518 tim1_brk_tim9
0x08000488 i2c2_ev 0x08000518 i2c2_ev
0x08000488 otg_fs_wkup 0x08000518 otg_fs_wkup
0x08000488 spi4 0x08000518 spi4
0x08000488 dma2_stream2 0x08000518 dma2_stream2
0x08000488 tim1_cc 0x08000518 tim1_cc
0x08000488 tim1_trg_com_tim11 0x08000518 tim1_trg_com_tim11
0x08000488 exti9_5 0x08000518 exti9_5
0x08000488 dma1_stream3 0x08000518 dma1_stream3
0x08000488 dma2_stream4 0x08000518 dma2_stream4
0x08000488 i2c2_er 0x08000518 i2c2_er
0x08000488 dma2_stream7 0x08000518 dma2_stream7
0x08000488 dma1_stream7 0x08000518 dma1_stream7
0x08000488 nmi 0x08000518 nmi
0x08000488 systick 0x08000518 systick
0x08000488 tim4 0x08000518 tim4
0x08000488 tim5 0x08000518 tim5
0x08000488 dma1_stream4 0x08000518 dma1_stream4
.text.tim4_init .text.tim4_init
0x08000490 0x40 build/timer.o 0x08000520 0x40 build/timer.o
0x08000490 tim4_init 0x08000520 tim4_init
.text.tim4_start .text.tim4_start
0x080004d0 0x20 build/timer.o 0x08000560 0x20 build/timer.o
0x080004d0 tim4_start 0x08000560 tim4_start
.text.usart2_init
0x08000580 0x100 build/usart.o
0x08000580 usart2_init
.text.usart2_start
0x08000680 0x20 build/usart.o
0x08000680 usart2_start
.text.usart2_write_byte
0x080006a0 0x30 build/usart.o
0x080006a0 usart2_write_byte
.text.usart2_write
0x080006d0 0x2a build/usart.o
0x080006d0 usart2_write
*(.rodata) *(.rodata)
*fill* 0x080006fa 0x2
.rodata 0x080006fc 0xf build/main.o
*(.rodata.*) *(.rodata.*)
0x080004f0 . = ALIGN (0x4) 0x0800070c . = ALIGN (0x4)
0x080004f0 _data_addr = LOADADDR (.data) *fill* 0x0800070b 0x1
0x0800070c _data_addr = LOADADDR (.data)
.glue_7 0x080004f0 0x0 .glue_7 0x0800070c 0x0
.glue_7 0x080004f0 0x0 linker stubs .glue_7 0x0800070c 0x0 linker stubs
.glue_7t 0x080004f0 0x0 .glue_7t 0x0800070c 0x0
.glue_7t 0x080004f0 0x0 linker stubs .glue_7t 0x0800070c 0x0 linker stubs
.vfp11_veneer 0x080004f0 0x0 .vfp11_veneer 0x0800070c 0x0
.vfp11_veneer 0x080004f0 0x0 linker stubs .vfp11_veneer 0x0800070c 0x0 linker stubs
.v4_bx 0x080004f0 0x0 .v4_bx 0x0800070c 0x0
.v4_bx 0x080004f0 0x0 linker stubs .v4_bx 0x0800070c 0x0 linker stubs
.iplt 0x080004f0 0x0 .iplt 0x0800070c 0x0
.iplt 0x080004f0 0x0 build/main.o .iplt 0x0800070c 0x0 build/main.o
.rel.dyn 0x080004f0 0x0 .rel.dyn 0x0800070c 0x0
.rel.iplt 0x080004f0 0x0 build/main.o .rel.iplt 0x0800070c 0x0 build/main.o
.data 0x20000000 0x0 load address 0x080004f0 .data 0x20000000 0x0 load address 0x0800070c
0x20000000 . = ALIGN (0x4) 0x20000000 . = ALIGN (0x4)
0x20000000 _data_start = . 0x20000000 _data_start = .
*(.data) *(.data)
@@ -248,10 +302,10 @@ LOAD build/timer.o
0x20000000 . = ALIGN (0x4) 0x20000000 . = ALIGN (0x4)
0x20000000 _data_end = . 0x20000000 _data_end = .
.igot.plt 0x20000000 0x0 load address 0x080004f0 .igot.plt 0x20000000 0x0 load address 0x0800070c
.igot.plt 0x20000000 0x0 build/main.o .igot.plt 0x20000000 0x0 build/main.o
.bss 0x20000000 0x0 load address 0x080004f0 .bss 0x20000000 0x0 load address 0x0800070c
0x20000000 . = ALIGN (0x4) 0x20000000 . = ALIGN (0x4)
0x20000000 _bss_start = . 0x20000000 _bss_start = .
*(.bss) *(.bss)
@@ -261,40 +315,46 @@ LOAD build/timer.o
OUTPUT(build/final.elf elf32-littlearm) OUTPUT(build/final.elf elf32-littlearm)
LOAD linker stubs LOAD linker stubs
.debug_info 0x00000000 0xb25 .debug_info 0x00000000 0xf2b
.debug_info 0x00000000 0x21a build/gpio.o .debug_info 0x00000000 0x262 build/gpio.o
.debug_info 0x0000021a 0x44e build/main.o .debug_info 0x00000262 0x47e build/main.o
.debug_info 0x00000668 0x188 build/startup.o .debug_info 0x000006e0 0x188 build/startup.o
.debug_info 0x000007f0 0x335 build/timer.o .debug_info 0x00000868 0x335 build/timer.o
.debug_info 0x00000b9d 0x38e build/usart.o
.debug_abbrev 0x00000000 0x44b .debug_abbrev 0x00000000 0x5ae
.debug_abbrev 0x00000000 0x12b build/gpio.o .debug_abbrev 0x00000000 0x11d build/gpio.o
.debug_abbrev 0x0000012b 0x144 build/main.o .debug_abbrev 0x0000011d 0x14b build/main.o
.debug_abbrev 0x0000026f 0x127 build/startup.o .debug_abbrev 0x00000268 0x127 build/startup.o
.debug_abbrev 0x00000396 0xb5 build/timer.o .debug_abbrev 0x0000038f 0xb5 build/timer.o
.debug_abbrev 0x00000444 0x16a build/usart.o
.debug_aranges 0x00000000 0xa8 .debug_aranges 0x00000000 0xe8
.debug_aranges .debug_aranges
0x00000000 0x28 build/gpio.o 0x00000000 0x30 build/gpio.o
.debug_aranges .debug_aranges
0x00000028 0x28 build/main.o 0x00000030 0x28 build/main.o
.debug_aranges .debug_aranges
0x00000050 0x30 build/startup.o 0x00000058 0x30 build/startup.o
.debug_aranges .debug_aranges
0x00000080 0x28 build/timer.o 0x00000088 0x28 build/timer.o
.debug_aranges
0x000000b0 0x38 build/usart.o
.debug_rnglists .debug_rnglists
0x00000000 0x6c 0x00000000 0x99
.debug_rnglists .debug_rnglists
0x00000000 0x19 build/gpio.o 0x00000000 0x20 build/gpio.o
.debug_rnglists .debug_rnglists
0x00000019 0x1b build/main.o 0x00000020 0x1b build/main.o
.debug_rnglists .debug_rnglists
0x00000034 0x1f build/startup.o 0x0000003b 0x1f build/startup.o
.debug_rnglists .debug_rnglists
0x00000053 0x19 build/timer.o 0x0000005a 0x19 build/timer.o
.debug_rnglists
0x00000073 0x26 build/usart.o
.debug_macro 0x00000000 0x3ba0 .debug_macro 0x00000000 0x48cd
.debug_macro 0x00000000 0xb56 build/gpio.o .debug_macro 0x00000000 0xb56 build/gpio.o
.debug_macro 0x00000b56 0x22 build/gpio.o .debug_macro 0x00000b56 0x22 build/gpio.o
.debug_macro 0x00000b78 0x75 build/gpio.o .debug_macro 0x00000b78 0x75 build/gpio.o
@@ -309,33 +369,39 @@ LOAD linker stubs
.debug_macro 0x0000108c 0x89 build/gpio.o .debug_macro 0x0000108c 0x89 build/gpio.o
.debug_macro 0x00001115 0x4cc build/gpio.o .debug_macro 0x00001115 0x4cc build/gpio.o
.debug_macro 0x000015e1 0x22 build/gpio.o .debug_macro 0x000015e1 0x22 build/gpio.o
.debug_macro 0x00001603 0x34 build/gpio.o .debug_macro 0x00001603 0x46 build/gpio.o
.debug_macro 0x00001637 0xb80 build/main.o .debug_macro 0x00001649 0xb89 build/main.o
.debug_macro 0x000021b7 0x12a build/main.o .debug_macro 0x000021d2 0x19e build/main.o
.debug_macro 0x000022e1 0x46 build/main.o .debug_macro 0x00002370 0x46 build/main.o
.debug_macro 0x00002327 0x2e build/main.o .debug_macro 0x000023b6 0x2e build/main.o
.debug_macro 0x00002355 0x22 build/main.o .debug_macro 0x000023e4 0x22 build/main.o
.debug_macro 0x00002377 0xb02 build/startup.o .debug_macro 0x00002406 0x76 build/main.o
.debug_macro 0x00002e79 0x56 build/startup.o .debug_macro 0x0000247c 0xb02 build/startup.o
.debug_macro 0x00002ecf 0x51 build/startup.o .debug_macro 0x00002f7e 0x56 build/startup.o
.debug_macro 0x00002f20 0xb5c build/timer.o .debug_macro 0x00002fd4 0x51 build/startup.o
.debug_macro 0x00003a7c 0x124 build/timer.o .debug_macro 0x00003025 0xb5c build/timer.o
.debug_macro 0x00003b81 0x198 build/timer.o
.debug_macro 0x00003d19 0xb74 build/usart.o
.debug_macro 0x0000488d 0x40 build/usart.o
.debug_line 0x00000000 0x4b9 .debug_line 0x00000000 0x6b6
.debug_line 0x00000000 0x116 build/gpio.o .debug_line 0x00000000 0x179 build/gpio.o
.debug_line 0x00000116 0x1da build/main.o .debug_line 0x00000179 0x1da build/main.o
.debug_line 0x000002f0 0xea build/startup.o .debug_line 0x00000353 0xea build/startup.o
.debug_line 0x000003da 0xdf build/timer.o .debug_line 0x0000043d 0xdf build/timer.o
.debug_line 0x0000051c 0x19a build/usart.o
.debug_str 0x00000000 0x5eb8 .debug_str 0x00000000 0x63f5
.debug_str 0x00000000 0x5372 build/gpio.o .debug_str 0x00000000 0x53d8 build/gpio.o
0x551a (size before relaxing) 0x5588 (size before relaxing)
.debug_str 0x00005372 0xab2 build/main.o .debug_str 0x000053d8 0xf48 build/main.o
0x5f7c (size before relaxing) 0x6462 (size before relaxing)
.debug_str 0x00005e24 0x88 build/startup.o .debug_str 0x00006320 0x88 build/startup.o
0x3cdf (size before relaxing) 0x3cdc (size before relaxing)
.debug_str 0x00005eac 0xc build/timer.o .debug_str 0x000063a8 0xc build/timer.o
0x5b1a (size before relaxing) 0x5d37 (size before relaxing)
.debug_str 0x000063b4 0x41 build/usart.o
0x6132 (size before relaxing)
.comment 0x00000000 0x45 .comment 0x00000000 0x45
.comment 0x00000000 0x45 build/gpio.o .comment 0x00000000 0x45 build/gpio.o
@@ -343,6 +409,7 @@ LOAD linker stubs
.comment 0x00000045 0x46 build/main.o .comment 0x00000045 0x46 build/main.o
.comment 0x00000045 0x46 build/startup.o .comment 0x00000045 0x46 build/startup.o
.comment 0x00000045 0x46 build/timer.o .comment 0x00000045 0x46 build/timer.o
.comment 0x00000045 0x46 build/usart.o
.ARM.attributes .ARM.attributes
0x00000000 0x34 0x00000000 0x34
@@ -354,24 +421,30 @@ LOAD linker stubs
0x00000068 0x34 build/startup.o 0x00000068 0x34 build/startup.o
.ARM.attributes .ARM.attributes
0x0000009c 0x34 build/timer.o 0x0000009c 0x34 build/timer.o
.ARM.attributes
0x000000d0 0x34 build/usart.o
.debug_line_str .debug_line_str
0x00000000 0x283 0x00000000 0x290
.debug_line_str .debug_line_str
0x00000000 0x24e build/gpio.o 0x00000000 0x24b build/gpio.o
0x260 (size before relaxing) 0x25d (size before relaxing)
.debug_line_str .debug_line_str
0x0000024e 0x23 build/main.o 0x0000024b 0x2b build/main.o
0x27c (size before relaxing) 0x281 (size before relaxing)
.debug_line_str .debug_line_str
0x00000271 0xa build/startup.o 0x00000276 0xa build/startup.o
0x21b (size before relaxing) 0x218 (size before relaxing)
.debug_line_str .debug_line_str
0x0000027b 0x8 build/timer.o 0x00000280 0x8 build/timer.o
0x25e (size before relaxing) 0x25b (size before relaxing)
.debug_line_str
0x00000288 0x8 build/usart.o
0x26c (size before relaxing)
.debug_frame 0x00000000 0x16c .debug_frame 0x00000000 0x234
.debug_frame 0x00000000 0x60 build/gpio.o .debug_frame 0x00000000 0x88 build/gpio.o
.debug_frame 0x00000060 0x50 build/main.o .debug_frame 0x00000088 0x50 build/main.o
.debug_frame 0x000000b0 0x6c build/startup.o .debug_frame 0x000000d8 0x6c build/startup.o
.debug_frame 0x0000011c 0x50 build/timer.o .debug_frame 0x00000144 0x50 build/timer.o
.debug_frame 0x00000194 0xa0 build/usart.o
build/gpio.S
+509 -336
View File
File diff suppressed because it is too large Load Diff
build/gpio.i
+30 -11
View File
@@ -1,5 +1,5 @@
# 0 "src/gpio.c" # 0 "src/gpio.c"
# 1 "/home/alex/code/own/c-compile-experiments//" # 1 "/home/alex/code/own/stm32-falling-sand//"
# 0 "<built-in>" # 0 "<built-in>"
#define __STDC__ 1 #define __STDC__ 1
# 0 "<built-in>" # 0 "<built-in>"
@@ -1995,17 +1995,23 @@ struct gpio {
volatile uint32_t ODR; volatile uint32_t ODR;
volatile uint32_t BSRR; volatile uint32_t BSRR;
volatile uint32_t LCKR; volatile uint32_t LCKR;
volatile uint32_t AFRL[2]; volatile uint32_t AFRL;
volatile uint32_t AFRH[2]; volatile uint32_t AFRH;
}; };
#define GPIO_AF_MCO_1 (0b0000)
#define GPIO_AF_USART2_RX (0b0111)
#define GPIO_AF_USART2_TX (0b0111)
#define GPIO_BASE_ADDR (0x40020000U) #define GPIO_BASE_ADDR (0x40020000U)
#define GPIO_PORT_OFFSET (0x400U) #define GPIO_PORT_OFFSET (0x400U)
#define GPIO(port) ((struct gpio*)(uintptr_t)(GPIO_BASE_ADDR + (GPIO_PORT_OFFSET * port))) #define GPIO(port) ((struct gpio*)(uintptr_t)(GPIO_BASE_ADDR + (GPIO_PORT_OFFSET * port)))
#define BIT(x) (1 << x)
#define PIN(port,num) ((((port) - 'A') << 8) | num) #define PORT(port) (((port) - 'A') << 8)
#define PIN(port,num) (PORT(port) | num)
#define PINNUM(pin) (pin & 0b1111) #define PINNUM(pin) (pin & 0b1111)
@@ -2019,24 +2025,37 @@ typedef enum {
} GPIO_MODE; } GPIO_MODE;
void gpio_set_mode(uint16_t pin, GPIO_MODE mode); void gpio_set_mode(uint16_t pin, GPIO_MODE mode);
void gpio_set_af(uint16_t pin, uint8_t af);
void gpio_write(uint16_t pin, void gpio_write(uint16_t pin,
# 40 "src/gpio.h" 3 4 # 47 "src/gpio.h" 3 4
_Bool _Bool
# 40 "src/gpio.h" # 47 "src/gpio.h"
val); val);
# 5 "src/gpio.c" 2 # 5 "src/gpio.c" 2
void gpio_set_mode(uint16_t pin, GPIO_MODE mode) { void gpio_set_mode(uint16_t pin, GPIO_MODE mode) {
struct gpio *gpio = ((struct gpio*)(uintptr_t)((0x40020000U) + ((0x400U) * (pin >> 8)))); struct gpio *gpio = ((struct gpio*)(uintptr_t)((0x40020000U) + ((0x400U) * (pin >> 8))));
int pn = (pin & 0b1111); int pn = (pin & 0b1111);
gpio->MODER &= ~(0x0011 << (pn * 2)); gpio->MODER &= ~(0b11 << (pn * 2));
gpio->MODER |= (mode & 0b011) << (pn * 2); gpio->MODER |= (mode & 0b11) << (pn * 2);
}
void gpio_set_af(uint16_t pin, uint8_t af) {
struct gpio *gpio = ((struct gpio*)(uintptr_t)((0x40020000U) + ((0x400U) * (pin >> 8))));
int pn = (pin & 0b1111);
if (pn < 8) {
gpio->AFRL &= ~(0b1111 << (pn * 4));
gpio->AFRL |= (af & 0b1111) << (pn * 4);
} else {
gpio->AFRH &= ~(0b1111 << (pn * 4));
gpio->AFRH |= (af & 0b1111) << (pn * 4);
}
} }
void gpio_write(uint16_t pin, void gpio_write(uint16_t pin,
# 13 "src/gpio.c" 3 4 # 25 "src/gpio.c" 3 4
_Bool _Bool
# 13 "src/gpio.c" # 25 "src/gpio.c"
val) { val) {
struct gpio *gpio = ((struct gpio*)(uintptr_t)((0x40020000U) + ((0x400U) * (pin >> 8)))); struct gpio *gpio = ((struct gpio*)(uintptr_t)((0x40020000U) + ((0x400U) * (pin >> 8))));
gpio->BSRR = (0b0011 << (pin & 0b1111)) << (val ? 0 : 16); gpio->BSRR = (0b0011 << (pin & 0b1111)) << (val ? 0 : 16);
build/gpio.o
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build/main.S
+836 -588
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build/main.i
+124 -23
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@@ -1,5 +1,5 @@
# 0 "src/main.c" # 0 "src/main.c"
# 1 "/home/alex/code/own/c-compile-experiments//" # 1 "/home/alex/code/own/stm32-falling-sand//"
# 0 "<built-in>" # 0 "<built-in>"
#define __STDC__ 1 #define __STDC__ 1
# 0 "<built-in>" # 0 "<built-in>"
@@ -2029,6 +2029,11 @@ struct rcc {
#define RCC_CR_PLLON_ON (1 << RCC_CR_PLLON_BIT) #define RCC_CR_PLLON_ON (1 << RCC_CR_PLLON_BIT)
#define RCC_CR_CSS_BIT 19
#define RCC_CR_CSS_ON (1 << RCC_CR_CSS_BIT)
#define RCC_CR_HSERDY_BIT 17 #define RCC_CR_HSERDY_BIT 17
#define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT) #define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT)
@@ -2051,6 +2056,7 @@ struct rcc {
#define RCC_PLLCFGR_PLLSRC_BIT 22 #define RCC_PLLCFGR_PLLSRC_BIT 22
#define RCC_PLLCFGR_PLLSRC_HSE (1 << RCC_PLLCFGR_PLLSRC_BIT) #define RCC_PLLCFGR_PLLSRC_HSE (1 << RCC_PLLCFGR_PLLSRC_BIT)
#define RCC_PLLCFGR_PLLSRC_HSI (0 << RCC_PLLCFGR_PLLSRC_BIT)
#define RCC_PLLCFGR_PLLP_BIT 16 #define RCC_PLLCFGR_PLLP_BIT 16
#define RCC_PLLCFGR_PLLP_MASK (0b11) #define RCC_PLLCFGR_PLLP_MASK (0b11)
@@ -2070,6 +2076,21 @@ struct rcc {
#define RCC_CFGR_PPRE_DIV_2 (0b100) #define RCC_CFGR_PPRE_DIV_2 (0b100)
#define RCC_CFGR_MCO1_HSI (0b00)
#define RCC_CFGR_MCO1_HSE (0b10)
#define RCC_CFGR_MCO1_PLL (0b11)
#define RCC_CFGR_MCO1_BIT 21
#define RCC_CFGR_MCO1_MASK (0b11)
#define RCC_CFGR_MCO1PRE_DIV5 (0b111)
#define RCC_CFGR_MCO1PRE_DIV4 (0b110)
#define RCC_CFGR_MCO1PRE_DIV2 (0b100)
#define RCC_CFGR_MCO1PRE_BIT 24
#define RCC_CFGR_MCO1PRE_MASK (0b111)
#define RCC_CFGR_PPRE2_BIT 13 #define RCC_CFGR_PPRE2_BIT 13
#define RCC_CFGR_PPRE2_MASK (0b111) #define RCC_CFGR_PPRE2_MASK (0b111)
@@ -2097,9 +2118,17 @@ struct rcc {
#define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT) #define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT)
#define RCC_AHB1ENR_GPIOAEN_BIT 0
#define RCC_AHB1ENR_GPIOAEN_ENABLE (1 << RCC_AHB1ENR_GPIOAEN_BIT)
#define RCC_APB1ENR_PWREN_BIT 28 #define RCC_APB1ENR_PWREN_BIT 28
#define RCC_APB1ENR_PWREN_CLOCK_ENABLE (1 << RCC_APB1ENR_PWREN_BIT) #define RCC_APB1ENR_PWREN_CLOCK_ENABLE (1 << RCC_APB1ENR_PWREN_BIT)
#define RCC_APB1ENR_USART2EN_BIT 17
#define RCC_APB1ENR_USART2EN_ENABLE (1 << RCC_APB1ENR_USART2EN_BIT)
#define RCC_APB1ENR_TIM4_BIT 2 #define RCC_APB1ENR_TIM4_BIT 2
#define RCC_APB1ENR_TIM4_ENABLE (1 << RCC_APB1ENR_TIM4_BIT) #define RCC_APB1ENR_TIM4_ENABLE (1 << RCC_APB1ENR_TIM4_BIT)
# 5 "src/main.c" 2 # 5 "src/main.c" 2
@@ -2119,17 +2148,23 @@ struct gpio {
volatile uint32_t ODR; volatile uint32_t ODR;
volatile uint32_t BSRR; volatile uint32_t BSRR;
volatile uint32_t LCKR; volatile uint32_t LCKR;
volatile uint32_t AFRL[2]; volatile uint32_t AFRL;
volatile uint32_t AFRH[2]; volatile uint32_t AFRH;
}; };
#define GPIO_AF_MCO_1 (0b0000)
#define GPIO_AF_USART2_RX (0b0111)
#define GPIO_AF_USART2_TX (0b0111)
#define GPIO_BASE_ADDR (0x40020000U) #define GPIO_BASE_ADDR (0x40020000U)
#define GPIO_PORT_OFFSET (0x400U) #define GPIO_PORT_OFFSET (0x400U)
#define GPIO(port) ((struct gpio*)(uintptr_t)(GPIO_BASE_ADDR + (GPIO_PORT_OFFSET * port))) #define GPIO(port) ((struct gpio*)(uintptr_t)(GPIO_BASE_ADDR + (GPIO_PORT_OFFSET * port)))
#define BIT(x) (1 << x)
#define PIN(port,num) ((((port) - 'A') << 8) | num) #define PORT(port) (((port) - 'A') << 8)
#define PIN(port,num) (PORT(port) | num)
#define PINNUM(pin) (pin & 0b1111) #define PINNUM(pin) (pin & 0b1111)
@@ -2143,10 +2178,11 @@ typedef enum {
} GPIO_MODE; } GPIO_MODE;
void gpio_set_mode(uint16_t pin, GPIO_MODE mode); void gpio_set_mode(uint16_t pin, GPIO_MODE mode);
void gpio_set_af(uint16_t pin, uint8_t af);
void gpio_write(uint16_t pin, void gpio_write(uint16_t pin,
# 40 "src/gpio.h" 3 4 # 47 "src/gpio.h" 3 4
_Bool _Bool
# 40 "src/gpio.h" # 47 "src/gpio.h"
val); val);
# 6 "src/main.c" 2 # 6 "src/main.c" 2
# 1 "src/flash.h" 1 # 1 "src/flash.h" 1
@@ -2177,7 +2213,7 @@ struct flash {
#define FLASH_ACR_ICEN_ENABLE (1 <<FLASH_ACR_ICEN_BIT) #define FLASH_ACR_ICEN_ENABLE (1 <<FLASH_ACR_ICEN_BIT)
#define FLASH_ACR_LATENCY_3_WAIT_STATES (0x0111) #define FLASH_ACR_LATENCY_3_WAIT_STATES (0b0011)
#define FLASH_ACR_LATENCY_BIT 0 #define FLASH_ACR_LATENCY_BIT 0
#define FLASH_ACR_LATENCY_MASK (0b1111) #define FLASH_ACR_LATENCY_MASK (0b1111)
@@ -2237,12 +2273,71 @@ struct timer {
#define TIM4_BASE_ADDR (0x40000800U) #define TIM4_BASE_ADDR (0x40000800U)
#define TIM4 ((struct timer *) TIM4_BASE_ADDR) #define TIM4 ((struct timer *) TIM4_BASE_ADDR)
#define TIM4_CR_CEN_BIT 0 #define TIM_CR1_CEN_BIT 0
#define TIM4_ENABLE (1 << TIM4_CR_CEN_BIT) #define TIM_ENABLE (1 << TIM_CR1_CEN_BIT)
void tim4_init(void); void tim4_init(void);
void tim4_start(void); void tim4_start(void);
# 9 "src/main.c" 2 # 9 "src/main.c" 2
# 1 "src/usart.h" 1
#define USART_H_
struct usart {
volatile uint32_t SR;
volatile uint32_t DR;
volatile uint32_t BRR;
volatile uint32_t CR1;
volatile uint32_t CR2;
volatile uint32_t CR3;
volatile uint32_t GTPR;
};
#define USART2_BASE_ADDR (0x40004400U)
#define USART2 ((struct usart *) USART2_BASE_ADDR)
#define USART_SR_TXE_BIT 7
#define USART_SR_TXE_TRANSMITTED (1 << USART_SR_TXE_BIT)
#define USART_SR_TC_BIT 6
#define USART_SR_TC_COMPLETED (1 << USART_SR_TC_BIT)
#define USART_SR_RXNE_BIT 5
#define USART_SR_RXNE_READY (1 <<USART_SR_RXNE_BIT)
#define USART_CR1_UE_BIT 13
#define USART_CR1_UE_ENABLE (1 << USART_CR1_UE_BIT)
#define USART_CR1_TE_BIT 3
#define USART_CR1_TE_ENABLE (1 << USART_CR1_TE_BIT)
#define USART_CR1_RE_BIT 2
#define USART_CR1_RE_ENABLE (1 << USART_CR1_RE_BIT)
#define USART_BRR_MANTISSA_BIT 4
#define USART_BRR_MANTISSA_MASK (0b111111111111)
#define USART_BRR_FRACTION_BIT 0
#define USART_BRR_FRACTION_MASK (0b111)
void usart2_init(void);
void usart2_start(void);
void usart2_write_byte(uint8_t byte);
void usart2_write(char *buf);
# 10 "src/main.c" 2
#define exit 42 #define exit 42
@@ -2255,9 +2350,14 @@ static void system_clock_init(void) {
((struct pwr *) (0x40007000U))->CR |= ((0b11) << 14); ((struct pwr *) (0x40007000U))->CR |= ((0b11) << 14);
((struct rcc *) (0x40023800U))->CR &= ~(1 << 0);
# 34 "src/main.c"
((struct rcc *) (0x40023800U))->CR |= (1 << 16); ((struct rcc *) (0x40023800U))->CR |= (1 << 16);
((struct rcc *) (0x40023800U))->CR |= (1 << 19);
while (!(((struct rcc *) (0x40023800U))->CR & (1 << 17))); while (!(((struct rcc *) (0x40023800U))->CR & (1 << 17)));
@@ -2269,7 +2369,7 @@ static void system_clock_init(void) {
((struct rcc *) (0x40023800U))->PLLCFGR |= (1 << 22); ((struct rcc *) (0x40023800U))->PLLCFGR |= (1 << 22);
((struct rcc *) (0x40023800U))->PLLCFGR |= ((25 & (0b111111)) << 0) | ((196 & (0b111111111)) << 6) | ((2 & (0b11)) << 16) | ((4 & (0b1111)) << 24); ((struct rcc *) (0x40023800U))->PLLCFGR |= ((25 & (0b111111)) << 0) | ((192 & (0b111111111)) << 6) | ((2 & (0b11)) << 16) | ((4 & (0b1111)) << 24);
((struct rcc *) (0x40023800U))->CFGR &= ~((0b1111) << 4); ((struct rcc *) (0x40023800U))->CFGR &= ~((0b1111) << 4);
@@ -2288,33 +2388,32 @@ static void system_clock_init(void) {
while (!(((struct rcc *) (0x40023800U))->CR & (1 << 17))); while (!(((struct rcc *) (0x40023800U))->CR & (1 << 25)));
((struct flash *) (0x40023C00U))->ACR |= (1 <<10); ((struct flash *) (0x40023C00U))->ACR |= (1 <<10);
((struct flash *) (0x40023C00U))->ACR |= (1 <<9); ((struct flash *) (0x40023C00U))->ACR |= (1 <<9);
((struct flash *) (0x40023C00U))->ACR &= ~((0b1111) << 0);
((struct rcc *) (0x40023800U))->CFGR |= ((0x0111) << 0);
((struct rcc *) (0x40023800U))->CFGR &= ~((0b11) << 0);
((struct rcc *) (0x40023800U))->CFGR |= ((0b10) << 0);
((struct rcc *) (0x40023800U))->CFGR |= (((0b10) & (0b11)) << 0);
while (((((struct rcc *) (0x40023800U))->CFGR >> 2) & (0b11)) != (0b10)); while (((((struct rcc *) (0x40023800U))->CFGR >> 2) & (0b11)) != (0b10));
((struct rcc *) (0x40023800U))->CR &= ~(1 << 0);
} }
int main(void) { int main(void) {
(void) system_clock_init(); (void) system_clock_init();
(void) tim4_init(); (void) tim4_init();
(void) usart2_init();
(void) tim4_start(); (void) tim4_start();
(void) usart2_start();
uint16_t led = (((('C') - 'A') << 8) | 13); uint16_t led = (((('C') - 'A') << 8) | 13);
((struct rcc *) (0x40023800U))->AHB1ENR |= (1 << (led >> 8)); ((struct rcc *) (0x40023800U))->AHB1ENR |= (1 << (led >> 8));
@@ -2322,19 +2421,21 @@ int main(void) {
uint16_t counter = ((struct timer *) (0x40000800U))->CNT; uint16_t counter = ((struct timer *) (0x40000800U))->CNT;
# 87 "src/main.c" 3 4 # 102 "src/main.c" 3 4
_Bool _Bool
# 87 "src/main.c" # 102 "src/main.c"
led_on = led_on =
# 87 "src/main.c" 3 4 # 102 "src/main.c" 3 4
((_Bool)+0u) ((_Bool)+0u)
# 87 "src/main.c" # 102 "src/main.c"
; ;
while(1) { while(1) {
if ((((struct timer *) (0x40000800U))->CNT - counter) >= 250) { if ((((struct timer *) (0x40000800U))->CNT - counter) >= 250) {
led_on = !led_on; led_on = !led_on;
gpio_write(led, led_on); gpio_write(led, led_on);
usart2_write("hello, world!\n");
counter = ((struct timer *) (0x40000800U))->CNT; counter = ((struct timer *) (0x40000800U))->CNT;
} }
}; };
build/main.o
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build/startup.S
+16 -16
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@@ -2923,6 +2923,8 @@ interrupt_vector_table:
.ascii "INOR__ >= ((maj) << 16) + (min))\000" .ascii "INOR__ >= ((maj) << 16) + (min))\000"
.LASF171: .LASF171:
.ascii "__DBL_MAX__ ((double)1.7976931348623157e+308L)\000" .ascii "__DBL_MAX__ ((double)1.7976931348623157e+308L)\000"
.LASF602:
.ascii "UINTMAX_C(x) __UINTMAX_C(x)\000"
.LASF253: .LASF253:
.ascii "__USFRACT_MIN__ 0.0UHR\000" .ascii "__USFRACT_MIN__ 0.0UHR\000"
.LASF578: .LASF578:
@@ -3020,8 +3022,8 @@ interrupt_vector_table:
.ascii "__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__\000" .ascii "__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__\000"
.LASF200: .LASF200:
.ascii "__FLT32_MIN_10_EXP__ (-37)\000" .ascii "__FLT32_MIN_10_EXP__ (-37)\000"
.LASF176: .LASF492:
.ascii "__DBL_HAS_DENORM__ 1\000" .ascii "__int20\000"
.LASF267: .LASF267:
.ascii "__LFRACT_IBIT__ 0\000" .ascii "__LFRACT_IBIT__ 0\000"
.LASF497: .LASF497:
@@ -3106,8 +3108,8 @@ interrupt_vector_table:
.ascii "__ARM_NEON\000" .ascii "__ARM_NEON\000"
.LASF401: .LASF401:
.ascii "__ARM_FEATURE_CMSE\000" .ascii "__ARM_FEATURE_CMSE\000"
.LASF625: .LASF68:
.ascii "/home/alex/code/own/c-compile-experiments\000" .ascii "__UINTPTR_TYPE__ unsigned int\000"
.LASF229: .LASF229:
.ascii "__FLT64_IS_IEC_60559__ 2\000" .ascii "__FLT64_IS_IEC_60559__ 2\000"
.LASF209: .LASF209:
@@ -3473,8 +3475,6 @@ interrupt_vector_table:
.ascii "UINT16_C(x) __UINT16_C(x)\000" .ascii "UINT16_C(x) __UINT16_C(x)\000"
.LASF344: .LASF344:
.ascii "__UTQ_FBIT__ 128\000" .ascii "__UTQ_FBIT__ 128\000"
.LASF499:
.ascii "__int20 +2\000"
.LASF610: .LASF610:
.ascii "long long int\000" .ascii "long long int\000"
.LASF24: .LASF24:
@@ -3539,8 +3539,8 @@ interrupt_vector_table:
.ascii "__STDC__ 1\000" .ascii "__STDC__ 1\000"
.LASF17: .LASF17:
.ascii "__SIZEOF_LONG__ 4\000" .ascii "__SIZEOF_LONG__ 4\000"
.LASF492: .LASF499:
.ascii "__int20\000" .ascii "__int20 +2\000"
.LASF168: .LASF168:
.ascii "__DBL_MAX_EXP__ 1024\000" .ascii "__DBL_MAX_EXP__ 1024\000"
.LASF585: .LASF585:
@@ -3567,6 +3567,8 @@ interrupt_vector_table:
.ascii "__SCHAR_WIDTH__ 8\000" .ascii "__SCHAR_WIDTH__ 8\000"
.LASF298: .LASF298:
.ascii "__ACCUM_MIN__ (-0X1P15K-0X1P15K)\000" .ascii "__ACCUM_MIN__ (-0X1P15K-0X1P15K)\000"
.LASF40:
.ascii "__CHAR16_TYPE__ short unsigned int\000"
.LASF21: .LASF21:
.ascii "__SIZEOF_DOUBLE__ 8\000" .ascii "__SIZEOF_DOUBLE__ 8\000"
.LASF7: .LASF7:
@@ -3801,8 +3803,8 @@ interrupt_vector_table:
.ascii "SIZE_MAX (__SIZE_MAX__)\000" .ascii "SIZE_MAX (__SIZE_MAX__)\000"
.LASF54: .LASF54:
.ascii "__INT_LEAST64_TYPE__ long long int\000" .ascii "__INT_LEAST64_TYPE__ long long int\000"
.LASF602: .LASF128:
.ascii "UINTMAX_C(x) __UINTMAX_C(x)\000" .ascii "__INT_FAST16_MAX__ 0x7fffffff\000"
.LASF49: .LASF49:
.ascii "__UINT32_TYPE__ long unsigned int\000" .ascii "__UINT32_TYPE__ long unsigned int\000"
.LASF183: .LASF183:
@@ -3879,8 +3881,8 @@ interrupt_vector_table:
.ascii "INT64_MAX (__INT64_MAX__)\000" .ascii "INT64_MAX (__INT64_MAX__)\000"
.LASF518: .LASF518:
.ascii "_INT8_T_DECLARED \000" .ascii "_INT8_T_DECLARED \000"
.LASF40: .LASF625:
.ascii "__CHAR16_TYPE__ short unsigned int\000" .ascii "/home/alex/code/own/stm32-falling-sand\000"
.LASF370: .LASF370:
.ascii "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1\000" .ascii "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1\000"
.LASF151: .LASF151:
@@ -4044,8 +4046,8 @@ interrupt_vector_table:
.ascii "__FLT32X_MAX_10_EXP__ 308\000" .ascii "__FLT32X_MAX_10_EXP__ 308\000"
.LASF140: .LASF140:
.ascii "__UINTPTR_MAX__ 0xffffffffU\000" .ascii "__UINTPTR_MAX__ 0xffffffffU\000"
.LASF128: .LASF176:
.ascii "__INT_FAST16_MAX__ 0x7fffffff\000" .ascii "__DBL_HAS_DENORM__ 1\000"
.LASF32: .LASF32:
.ascii "__GNUC_EXECUTION_CHARSET_NAME \"UTF-8\"\000" .ascii "__GNUC_EXECUTION_CHARSET_NAME \"UTF-8\"\000"
.LASF475: .LASF475:
@@ -4072,8 +4074,6 @@ interrupt_vector_table:
.ascii "long +4\000" .ascii "long +4\000"
.LASF534: .LASF534:
.ascii "__int_least8_t_defined 1\000" .ascii "__int_least8_t_defined 1\000"
.LASF68:
.ascii "__UINTPTR_TYPE__ unsigned int\000"
.LASF92: .LASF92:
.ascii "__UINTMAX_MAX__ 0xffffffffffffffffULL\000" .ascii "__UINTMAX_MAX__ 0xffffffffffffffffULL\000"
.LASF42: .LASF42:
build/startup.i
+1 -1
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@@ -1,5 +1,5 @@
# 0 "src/startup.c" # 0 "src/startup.c"
# 1 "/home/alex/code/own/c-compile-experiments//" # 1 "/home/alex/code/own/stm32-falling-sand//"
# 0 "<built-in>" # 0 "<built-in>"
#define __STDC__ 1 #define __STDC__ 1
# 0 "<built-in>" # 0 "<built-in>"
build/startup.o
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build/timer.S
+300 -212
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build/timer.i
+33 -4
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@@ -1,5 +1,5 @@
# 0 "src/timer.c" # 0 "src/timer.c"
# 1 "/home/alex/code/own/c-compile-experiments//" # 1 "/home/alex/code/own/stm32-falling-sand//"
# 0 "<built-in>" # 0 "<built-in>"
#define __STDC__ 1 #define __STDC__ 1
# 0 "<built-in>" # 0 "<built-in>"
@@ -2014,6 +2014,11 @@ struct rcc {
#define RCC_CR_PLLON_ON (1 << RCC_CR_PLLON_BIT) #define RCC_CR_PLLON_ON (1 << RCC_CR_PLLON_BIT)
#define RCC_CR_CSS_BIT 19
#define RCC_CR_CSS_ON (1 << RCC_CR_CSS_BIT)
#define RCC_CR_HSERDY_BIT 17 #define RCC_CR_HSERDY_BIT 17
#define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT) #define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT)
@@ -2036,6 +2041,7 @@ struct rcc {
#define RCC_PLLCFGR_PLLSRC_BIT 22 #define RCC_PLLCFGR_PLLSRC_BIT 22
#define RCC_PLLCFGR_PLLSRC_HSE (1 << RCC_PLLCFGR_PLLSRC_BIT) #define RCC_PLLCFGR_PLLSRC_HSE (1 << RCC_PLLCFGR_PLLSRC_BIT)
#define RCC_PLLCFGR_PLLSRC_HSI (0 << RCC_PLLCFGR_PLLSRC_BIT)
#define RCC_PLLCFGR_PLLP_BIT 16 #define RCC_PLLCFGR_PLLP_BIT 16
#define RCC_PLLCFGR_PLLP_MASK (0b11) #define RCC_PLLCFGR_PLLP_MASK (0b11)
@@ -2055,6 +2061,21 @@ struct rcc {
#define RCC_CFGR_PPRE_DIV_2 (0b100) #define RCC_CFGR_PPRE_DIV_2 (0b100)
#define RCC_CFGR_MCO1_HSI (0b00)
#define RCC_CFGR_MCO1_HSE (0b10)
#define RCC_CFGR_MCO1_PLL (0b11)
#define RCC_CFGR_MCO1_BIT 21
#define RCC_CFGR_MCO1_MASK (0b11)
#define RCC_CFGR_MCO1PRE_DIV5 (0b111)
#define RCC_CFGR_MCO1PRE_DIV4 (0b110)
#define RCC_CFGR_MCO1PRE_DIV2 (0b100)
#define RCC_CFGR_MCO1PRE_BIT 24
#define RCC_CFGR_MCO1PRE_MASK (0b111)
#define RCC_CFGR_PPRE2_BIT 13 #define RCC_CFGR_PPRE2_BIT 13
#define RCC_CFGR_PPRE2_MASK (0b111) #define RCC_CFGR_PPRE2_MASK (0b111)
@@ -2082,9 +2103,17 @@ struct rcc {
#define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT) #define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT)
#define RCC_AHB1ENR_GPIOAEN_BIT 0
#define RCC_AHB1ENR_GPIOAEN_ENABLE (1 << RCC_AHB1ENR_GPIOAEN_BIT)
#define RCC_APB1ENR_PWREN_BIT 28 #define RCC_APB1ENR_PWREN_BIT 28
#define RCC_APB1ENR_PWREN_CLOCK_ENABLE (1 << RCC_APB1ENR_PWREN_BIT) #define RCC_APB1ENR_PWREN_CLOCK_ENABLE (1 << RCC_APB1ENR_PWREN_BIT)
#define RCC_APB1ENR_USART2EN_BIT 17
#define RCC_APB1ENR_USART2EN_ENABLE (1 << RCC_APB1ENR_USART2EN_BIT)
#define RCC_APB1ENR_TIM4_BIT 2 #define RCC_APB1ENR_TIM4_BIT 2
#define RCC_APB1ENR_TIM4_ENABLE (1 << RCC_APB1ENR_TIM4_BIT) #define RCC_APB1ENR_TIM4_ENABLE (1 << RCC_APB1ENR_TIM4_BIT)
# 2 "src/timer.c" 2 # 2 "src/timer.c" 2
@@ -2120,8 +2149,8 @@ struct timer {
#define TIM4_BASE_ADDR (0x40000800U) #define TIM4_BASE_ADDR (0x40000800U)
#define TIM4 ((struct timer *) TIM4_BASE_ADDR) #define TIM4 ((struct timer *) TIM4_BASE_ADDR)
#define TIM4_CR_CEN_BIT 0 #define TIM_CR1_CEN_BIT 0
#define TIM4_ENABLE (1 << TIM4_CR_CEN_BIT) #define TIM_ENABLE (1 << TIM_CR1_CEN_BIT)
void tim4_init(void); void tim4_init(void);
void tim4_start(void); void tim4_start(void);
@@ -2137,7 +2166,7 @@ void tim4_init(void) {
((struct timer *) (0x40000800U))->PSC = (uint16_t) 48000 - 1; ((struct timer *) (0x40000800U))->PSC = (uint16_t) 96000 - 1;
((struct timer *) (0x40000800U))->ARR = (uint16_t) 0xFFFF; ((struct timer *) (0x40000800U))->ARR = (uint16_t) 0xFFFF;
build/timer.o
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build/usart.S
+6341
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build/usart.i
+2303
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build/usart.o
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src/flash.h
+1 -1
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@@ -25,7 +25,7 @@ struct flash {
#define FLASH_ACR_ICEN_ENABLE (1 <<FLASH_ACR_ICEN_BIT) #define FLASH_ACR_ICEN_ENABLE (1 <<FLASH_ACR_ICEN_BIT)
// Latency // Latency
#define FLASH_ACR_LATENCY_3_WAIT_STATES (0x0111) #define FLASH_ACR_LATENCY_3_WAIT_STATES (0b0011)
#define FLASH_ACR_LATENCY_BIT 0 // Bits [3:0] #define FLASH_ACR_LATENCY_BIT 0 // Bits [3:0]
#define FLASH_ACR_LATENCY_MASK (0b1111) #define FLASH_ACR_LATENCY_MASK (0b1111)
src/gpio.c
+14 -2
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@@ -6,8 +6,20 @@
void gpio_set_mode(uint16_t pin, GPIO_MODE mode) { void gpio_set_mode(uint16_t pin, GPIO_MODE mode) {
struct gpio *gpio = GPIO(PINPORT(pin)); // GPIO port address struct gpio *gpio = GPIO(PINPORT(pin)); // GPIO port address
int pn = PINNUM(pin); // Pin number int pn = PINNUM(pin); // Pin number
gpio->MODER &= ~(0x0011 << (pn * 2)); // Clear existing setting. Each pin uses 2 bits gpio->MODER &= ~(0b11 << (pn * 2)); // Clear existing setting. Each pin uses 2 bits
gpio->MODER |= (mode & 0b011) << (pn * 2); // Set new mode. Each pin uses 2 bits gpio->MODER |= (mode & 0b11) << (pn * 2); // Set new mode. Each pin uses 2 bits
}
void gpio_set_af(uint16_t pin, uint8_t af) {
struct gpio *gpio = GPIO(PINPORT(pin));
int pn = PINNUM(pin);
if (pn < 8) {
gpio->AFRL &= ~(0b1111 << (pn * 4)); // Each pin uses 4 bits
gpio->AFRL |= (af & 0b1111) << (pn * 4);
} else {
gpio->AFRH &= ~(0b1111 << (pn * 4)); // Each pin uses 4 bits
gpio->AFRH |= (af & 0b1111) << (pn * 4);
}
} }
void gpio_write(uint16_t pin, bool val) { void gpio_write(uint16_t pin, bool val) {
src/gpio.h
+9 -2
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@@ -17,13 +17,19 @@ struct gpio {
volatile uint32_t AFRH; // Alternative function high register volatile uint32_t AFRH; // Alternative function high register
}; };
// AFRH, AFRL registers
#define GPIO_AF_MCO_1 (0b0000) // Alternative function 0 (AF0)
#define GPIO_AF_USART2_RX (0b0111) // Alternative function 7 (AF7)
#define GPIO_AF_USART2_TX (0b0111) // Alternative function 7 (AF7)
#define GPIO_BASE_ADDR (0x40020000U) #define GPIO_BASE_ADDR (0x40020000U)
#define GPIO_PORT_OFFSET (0x400U) #define GPIO_PORT_OFFSET (0x400U)
#define GPIO(port) ((struct gpio*)(uintptr_t)(GPIO_BASE_ADDR + (GPIO_PORT_OFFSET * port))) #define GPIO(port) ((struct gpio*)(uintptr_t)(GPIO_BASE_ADDR + (GPIO_PORT_OFFSET * port)))
#define BIT(x) (1 << x) // Create a 8bit number from a port
#define PORT(port) (((port) - 'A') << 8)
// Create a 16bit number from a port and pin // Create a 16bit number from a port and pin
#define PIN(port, num) ((((port) - 'A') << 8) | num) #define PIN(port, num) (PORT(port) | num)
// get the lower byte from a PIN // get the lower byte from a PIN
#define PINNUM(pin) (pin & 0b1111) #define PINNUM(pin) (pin & 0b1111)
// get the upper byte from a PIN // get the upper byte from a PIN
@@ -37,6 +43,7 @@ typedef enum {
} GPIO_MODE; } GPIO_MODE;
void gpio_set_mode(uint16_t pin, GPIO_MODE mode); void gpio_set_mode(uint16_t pin, GPIO_MODE mode);
void gpio_set_af(uint16_t pin, uint8_t af);
void gpio_write(uint16_t pin, bool val); void gpio_write(uint16_t pin, bool val);
#endif #endif
src/main.c
+12 -3
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@@ -6,6 +6,7 @@
#include "flash.h" #include "flash.h"
#include "pwr.h" #include "pwr.h"
#include "timer.h" #include "timer.h"
#include "usart.h"
#define exit 42 #define exit 42
@@ -23,6 +24,9 @@ static void system_clock_init(void) {
// Turn on HSE // Turn on HSE
RCC->CR |= RCC_CR_HSEON_ON; RCC->CR |= RCC_CR_HSEON_ON;
// Turn on clock security system
RCC->CR |= RCC_CR_CSS_ON;
// Wait indefinitely for HSE to be ready // Wait indefinitely for HSE to be ready
// TODO indicate error/timeout somehow? // TODO indicate error/timeout somehow?
while (!(RCC->CR & RCC_CR_HSERDY_READY)); while (!(RCC->CR & RCC_CR_HSERDY_READY));
@@ -60,9 +64,10 @@ static void system_clock_init(void) {
FLASH->ACR |= FLASH_ACR_DCEN_ENABLE; FLASH->ACR |= FLASH_ACR_DCEN_ENABLE;
FLASH->ACR |= FLASH_ACR_ICEN_ENABLE; FLASH->ACR |= FLASH_ACR_ICEN_ENABLE;
// TODO breaks with these flash settings on; turning off for now
// Set latency to be 3 wait states (TODO: understand why exactly 3) // Set latency to be 3 wait states (TODO: understand why exactly 3)
FLASH->ACR &= ~(FLASH_ACR_LATENCY_MASK << FLASH_ACR_LATENCY_BIT); /* FLASH->ACR &= ~(FLASH_ACR_LATENCY_MASK << FLASH_ACR_LATENCY_BIT); */
RCC->CFGR |= (FLASH_ACR_LATENCY_3_WAIT_STATES << FLASH_ACR_LATENCY_BIT); /* RCC->CFGR |= (FLASH_ACR_LATENCY_3_WAIT_STATES << FLASH_ACR_LATENCY_BIT); */
// Use PLL as system clock // Use PLL as system clock
RCC->CFGR |= RCC_CFGR_SW(RCC_CFGR_SW_PLL); RCC->CFGR |= RCC_CFGR_SW(RCC_CFGR_SW_PLL);
@@ -75,11 +80,13 @@ static void system_clock_init(void) {
int main(void) { int main(void) {
(void) system_clock_init(); (void) system_clock_init();
(void) tim4_init(); (void) tim4_init();
(void) usart2_init();
(void) tim4_start(); (void) tim4_start();
(void) usart2_start();
uint16_t led = PIN('C', 13); // Blue LED uint16_t led = PIN('C', 13); // Blue LED
RCC->AHB1ENR |= BIT(PINPORT(led)); // Enable GPIO clock for LED RCC->AHB1ENR |= (1 << PINPORT(led)); // Enable GPIO clock for LED
gpio_set_mode(led, GPIO_MODE_OUTPUT); // Set blue LED to output mode gpio_set_mode(led, GPIO_MODE_OUTPUT); // Set blue LED to output mode
uint16_t counter = TIM4->CNT; uint16_t counter = TIM4->CNT;
@@ -89,6 +96,8 @@ int main(void) {
led_on = !led_on; led_on = !led_on;
gpio_write(led, led_on); gpio_write(led, led_on);
usart2_write("hello, world!\n");
counter = TIM4->CNT; counter = TIM4->CNT;
} }
}; };
src/rcc.h
+29
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@@ -46,6 +46,11 @@ struct rcc {
#define RCC_CR_PLLON_BIT 24 #define RCC_CR_PLLON_BIT 24
#define RCC_CR_PLLON_ON (1 << RCC_CR_PLLON_BIT) #define RCC_CR_PLLON_ON (1 << RCC_CR_PLLON_BIT)
// Clock security system
#define RCC_CR_CSS_BIT 19
#define RCC_CR_CSS_ON (1 << RCC_CR_CSS_BIT)
// HSE clock ready flag // HSE clock ready flag
#define RCC_CR_HSERDY_BIT 17 #define RCC_CR_HSERDY_BIT 17
#define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT) #define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT)
@@ -69,6 +74,7 @@ struct rcc {
#define RCC_PLLCFGR_PLLSRC_BIT 22 #define RCC_PLLCFGR_PLLSRC_BIT 22
#define RCC_PLLCFGR_PLLSRC_HSE (1 << RCC_PLLCFGR_PLLSRC_BIT) #define RCC_PLLCFGR_PLLSRC_HSE (1 << RCC_PLLCFGR_PLLSRC_BIT)
#define RCC_PLLCFGR_PLLSRC_HSI (0 << RCC_PLLCFGR_PLLSRC_BIT)
#define RCC_PLLCFGR_PLLP_BIT 16 // Bits [17:16] #define RCC_PLLCFGR_PLLP_BIT 16 // Bits [17:16]
#define RCC_PLLCFGR_PLLP_MASK (0b11) #define RCC_PLLCFGR_PLLP_MASK (0b11)
@@ -87,6 +93,21 @@ struct rcc {
#define RCC_CFGR_PPRE_DIV_NONE 0 #define RCC_CFGR_PPRE_DIV_NONE 0
#define RCC_CFGR_PPRE_DIV_2 (0b100) #define RCC_CFGR_PPRE_DIV_2 (0b100)
// Microcontroller clock output 1
#define RCC_CFGR_MCO1_HSI (0b00)
#define RCC_CFGR_MCO1_HSE (0b10)
#define RCC_CFGR_MCO1_PLL (0b11)
#define RCC_CFGR_MCO1_BIT 21 // Bits [22:21]
#define RCC_CFGR_MCO1_MASK (0b11)
#define RCC_CFGR_MCO1PRE_DIV5 (0b111)
#define RCC_CFGR_MCO1PRE_DIV4 (0b110)
#define RCC_CFGR_MCO1PRE_DIV2 (0b100)
#define RCC_CFGR_MCO1PRE_BIT 24 // Bits [26:24]
#define RCC_CFGR_MCO1PRE_MASK (0b111)
// APB2 // APB2
#define RCC_CFGR_PPRE2_BIT 13 // Bits [15:13] #define RCC_CFGR_PPRE2_BIT 13 // Bits [15:13]
#define RCC_CFGR_PPRE2_MASK (0b111) #define RCC_CFGR_PPRE2_MASK (0b111)
@@ -114,10 +135,18 @@ struct rcc {
#define RCC_CFGR_SW_MASK (0b11) #define RCC_CFGR_SW_MASK (0b11)
#define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT) #define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT)
// AHB1ENR Register
// GPIOA AHB1ENR
#define RCC_AHB1ENR_GPIOAEN_BIT 0
#define RCC_AHB1ENR_GPIOAEN_ENABLE (1 << RCC_AHB1ENR_GPIOAEN_BIT)
// APB1ENR Register // APB1ENR Register
#define RCC_APB1ENR_PWREN_BIT 28 #define RCC_APB1ENR_PWREN_BIT 28
#define RCC_APB1ENR_PWREN_CLOCK_ENABLE (1 << RCC_APB1ENR_PWREN_BIT) #define RCC_APB1ENR_PWREN_CLOCK_ENABLE (1 << RCC_APB1ENR_PWREN_BIT)
#define RCC_APB1ENR_USART2EN_BIT 17
#define RCC_APB1ENR_USART2EN_ENABLE (1 << RCC_APB1ENR_USART2EN_BIT)
#define RCC_APB1ENR_TIM4_BIT 2 #define RCC_APB1ENR_TIM4_BIT 2
#define RCC_APB1ENR_TIM4_ENABLE (1 << RCC_APB1ENR_TIM4_BIT) #define RCC_APB1ENR_TIM4_ENABLE (1 << RCC_APB1ENR_TIM4_BIT)
src/usart.c
+79
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@@ -0,0 +1,79 @@
#include "rcc.h"
#include "gpio.h"
#include "usart.h"
void usart2_init(void) {
// Enable clock for GPIOA as USART2 is on PORT A pins
RCC->AHB1ENR |= (1 << PORT('A'));
// Configure PA2 and PA3 (USART2 pins) to use alternative functions
// file:///home/alex/sync/org/stm32-sand/stm32f411ce.pdf#page=48
uint16_t txPin = PIN('A', 2);
gpio_set_mode(txPin, GPIO_MODE_AF);
gpio_set_af(txPin, GPIO_AF_USART2_TX);
uint16_t rxPin = PIN('A', 3);
gpio_set_mode(rxPin, GPIO_MODE_AF);
gpio_set_af(rxPin, GPIO_AF_USART2_RX);
// Configure PA8 to output HSE (MCO1)
uint16_t clockOutPin = PIN('A', 8);
gpio_set_mode(clockOutPin, GPIO_MODE_AF);
gpio_set_af(clockOutPin, GPIO_AF_MCO_1);
RCC->CFGR &= ~(RCC_CFGR_MCO1_MASK << RCC_CFGR_MCO1_BIT);
/* RCC->CFGR |= (RCC_CFGR_MCO1_HSE << RCC_CFGR_MCO1_BIT); */
RCC->CFGR |= (RCC_CFGR_MCO1_PLL << RCC_CFGR_MCO1_BIT);
RCC->CFGR &= ~(RCC_CFGR_MCO1PRE_MASK << RCC_CFGR_MCO1PRE_BIT);
RCC->CFGR |= (RCC_CFGR_MCO1PRE_DIV4 << RCC_CFGR_MCO1PRE_BIT);
// Enable USART
RCC->APB1ENR |= RCC_APB1ENR_USART2EN_ENABLE;
// Clear control registers
USART2->CR1 = 0;
USART2->CR2 = 0;
USART2->CR3 = 0;
// Calculate Baud rate:
// baud = f_clck / (8 * (2 - OVER8) * USARTDIV) =>
// (8 * (2 - OVER8) * USARTDIV) = f_clock / baud =>
// baud * (8 * (2 - OVER8) * USARTDIV) = f_clock =>
// USARTDIV = (f_clock / (baud * (8 * (2 - OVER8)))
// Target Baud rate = 115200, f_clock = 48MHz, OVER8 = 0
// USARTDIV = (48E6 / (115200 * (8 * 2))) = 26.0416666
// mantissa = 26 = 0x1A
// fraction = 0.041666 * 16 = 0.666656 ~= 1
// baud = 48E6 / (8 * 2 * 26) = 115384.61538461539
// error of 0.16% (115384.61538461539 / 115200 ) = 1.001602564102564
//
// skipping fractional part as error rate is good.
USART2->BRR &= ~(USART_BRR_MANTISSA_MASK << USART_BRR_MANTISSA_BIT);
USART2->BRR |= (0x1A << USART_BRR_MANTISSA_BIT);
USART2->BRR &= ~(USART_BRR_FRACTION_MASK << USART_BRR_FRACTION_BIT);
USART2->BRR |= (0x0 << USART_BRR_MANTISSA_BIT);
// Enable transmitter and receiver
USART2->CR1 |= USART_CR1_TE_ENABLE;
USART2->CR1 |= USART_CR1_RE_ENABLE;
}
void usart2_start(void) {
USART2->CR1 |= USART_CR1_UE_ENABLE;
}
void usart2_write_byte(uint8_t c) {
// Send data
USART2->DR = c;
// Wait indefinitely for transmission to be ready for data
/* while ((USART2->SR & USART_SR_TXE_TRANSMITTED) == 0); */
while (!(USART2->SR & USART_SR_TC_COMPLETED));
}
void usart2_write(char *buf) {
while (*buf) usart2_write_byte(*buf++);
}
src/usart.h
+59
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@@ -0,0 +1,59 @@
#ifndef USART_H_
#define USART_H_
#include <inttypes.h>
struct usart {
volatile uint32_t SR; // Status register
volatile uint32_t DR; // Data register
volatile uint32_t BRR; // Baud rate register
volatile uint32_t CR1; // Control register 1
volatile uint32_t CR2; // Control register 2
volatile uint32_t CR3; // Control register 3
volatile uint32_t GTPR; // Guard time and prescaler registe
};
#define USART2_BASE_ADDR (0x40004400U)
#define USART2 ((struct usart *) USART2_BASE_ADDR)
// SR Register
// Transmission data register empty
#define USART_SR_TXE_BIT 7
#define USART_SR_TXE_TRANSMITTED (1 << USART_SR_TXE_BIT)
// Transmission complete
#define USART_SR_TC_BIT 6
#define USART_SR_TC_COMPLETED (1 << USART_SR_TC_BIT)
// Read data register not empty
#define USART_SR_RXNE_BIT 5
#define USART_SR_RXNE_READY (1 <<USART_SR_RXNE_BIT)
// CR Register
// USART enable
#define USART_CR1_UE_BIT 13
#define USART_CR1_UE_ENABLE (1 << USART_CR1_UE_BIT)
// Trasmitter enable
#define USART_CR1_TE_BIT 3
#define USART_CR1_TE_ENABLE (1 << USART_CR1_TE_BIT)
// Receiver enable
#define USART_CR1_RE_BIT 2
#define USART_CR1_RE_ENABLE (1 << USART_CR1_RE_BIT)
// BRR Register
#define USART_BRR_MANTISSA_BIT 4 // Bits [15:4]
#define USART_BRR_MANTISSA_MASK (0b111111111111)
#define USART_BRR_FRACTION_BIT 0 // Bits [3:0]
#define USART_BRR_FRACTION_MASK (0b111)
void usart2_init(void);
void usart2_start(void);
void usart2_write_byte(uint8_t byte);
void usart2_write(char *buf);
#endif
todo.txt
+2
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@@ -0,0 +1,2 @@
- implement UART
- implement tim4 interrupt