diff --git a/build/final.elf b/build/final.elf
index 840b7af..5f46cac 100755
Binary files a/build/final.elf and b/build/final.elf differ
diff --git a/build/main.S b/build/main.S
index 4eb459c..2f2ba27 100644
--- a/build/main.S
+++ b/build/main.S
@@ -150,7 +150,7 @@ system_clock_init:
 	ldr	r3, .L5
 	ldr	r3, [r3]
 	.loc 1 54 47 discriminator 1
-	and	r3, r3, #131072
+	and	r3, r3, #33554432
 	.loc 1 54 10 discriminator 1
 	cmp	r3, #0
 	beq	.L3
diff --git a/build/main.i b/build/main.i
index e6e6844..5757b32 100644
--- a/build/main.i
+++ b/build/main.i
@@ -2288,7 +2288,7 @@ static void system_clock_init(void) {
 
 
 
-  while (!(((struct rcc *) (0x40023800U))->CR & (1 << 17)));
+  while (!(((struct rcc *) (0x40023800U))->CR & (1 << 25)));
 
 
   ((struct flash *) (0x40023C00U))->ACR |= (1 <<10);
diff --git a/build/main.o b/build/main.o
index 87460c9..7b6ef17 100644
Binary files a/build/main.o and b/build/main.o differ
diff --git a/src/main.c b/src/main.c
index 82c27f9..230a8e5 100644
--- a/src/main.c
+++ b/src/main.c
@@ -51,7 +51,7 @@ static void system_clock_init(void) {
 
   // Wait indefinitely for PLL to be ready
   // TODO indicate error/timeout somehow?
-  while (!(RCC->CR & RCC_CR_HSERDY_READY));
+  while (!(RCC->CR & RCC_CR_PLLRDY_LOCKED));
 
   // Enable caching of instructions and data
   FLASH->ACR |= FLASH_ACR_DCEN_ENABLE;