makefile: Add TARGET variable for final output file name
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5
Makefile
5
Makefile
@@ -21,6 +21,7 @@ LDFLAGS = -T link.ld -nostartfiles -nostdlib --specs nano.specs -lc -lgcc -Wl,--
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SRC_DIR = src
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BUILD_DIR = build
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TARGET = final
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SRC_FILES := $(wildcard $(SRC_DIR)/*.c)
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PREP_FILES := $(patsubst $(SRC_DIR)/%.c,$(BUILD_DIR)/%.i,$(SRC_FILES))
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@@ -28,9 +29,9 @@ ASM_FILES := $(patsubst $(BUILD_DIR)/%.i,$(BUILD_DIR)/%.S,$(PREP_FILES))
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OBJ_FILES := $(patsubst $(BUILD_DIR)/%.S,$(BUILD_DIR)/%.o,$(ASM_FILES))
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.PHONY: build
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build: builddir preprocess compile assemble $(BUILD_DIR)/final.elf
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build: builddir preprocess compile assemble $(BUILD_DIR)/$(TARGET).elf
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$(BUILD_DIR)/final.elf: $(OBJ_FILES)
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$(BUILD_DIR)/$(TARGET).elf: $(OBJ_FILES)
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$(CC) $(LDFLAGS) $^ -o $@
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$(BUILD_DIR)/%.i: $(SRC_DIR)/%.c
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