Configure system clock to run at 96Mhz

build/main.i

@@ -2012,14 +2012,9 @@ struct rcc {
 
 
 #define RCC_CR_PLLON_BIT 24
-#define RCC_CR_PLLON_OFF (0 << RCC_CR_PLLON_BIT)
 #define RCC_CR_PLLON_ON (1 << RCC_CR_PLLON_BIT)
 
 
-#define RCC_CR_HSEBYP_BIT 18
-#define RCC_CR_HSEBYP (1 << RCC_CR_HSEBYP_BIT)
-
-
 #define RCC_CR_HSERDY_BIT 17
 #define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT)
 
@@ -2027,8 +2022,13 @@ struct rcc {
 #define RCC_CR_HSEON_BIT 16
 #define RCC_CR_HSEON_ON (1 << RCC_CR_HSEON_BIT)
 
+
+#define RCC_CR_HSIRDY_BIT 1
+#define RCC_CR_HSIRDY_READY (1 << RCC_CR_HSIRDY_BIT)
+
+
 #define RCC_CR_HSION_BIT 0
-#define RCC_CR_HSION_OFF (0 << RCC_CR_HSION_BIT)
+#define RCC_CR_HSION_ON (1 << RCC_CR_HSION_BIT)
 
 
 #define RCC_PLLCFGR_PLLQ_BIT 24
@@ -2081,6 +2081,10 @@ struct rcc {
 #define RCC_CFGR_SW_BIT 0
 #define RCC_CFGR_SW_MASK (0b11)
 #define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT)
+
+
+#define RCC_APB1ENR_PWREN_BIT 28
+#define RCC_APB1ENR_PWREN_CLOCK_ENABLE (1 << RCC_APB1ENR_PWREN_BIT)
 # 3 "src/main.c" 2
 # 1 "src/gpio.h" 1
 
@@ -2140,28 +2144,150 @@ void gpio_write(uint16_t pin,
 # 40 "src/gpio.h"
                                   val);
 # 4 "src/main.c" 2
+# 1 "src/flash.h" 1
+
+#define FLASH_H_ 
+
+
+
+struct flash {
+  volatile uint32_t ACR;
+  volatile uint32_t KEYR;
+  volatile uint32_t OPTKEYR;
+  volatile uint32_t SR;
+  volatile uint32_t CR;
+  volatile uint32_t OPTCR;
+};
+
+#define FLASH_BASE_ADDR (0x40023C00U)
+#define FLASH ((struct flash *) FLASH_BASE_ADDR)
+
+
+
+#define FLASH_ACR_DCEN_BIT 10
+#define FLASH_ACR_DCEN_ENABLE (1 <<FLASH_ACR_DCEN_BIT)
+
+
+#define FLASH_ACR_ICEN_BIT 9
+#define FLASH_ACR_ICEN_ENABLE (1 <<FLASH_ACR_ICEN_BIT)
+
+
+#define FLASH_ACR_LATENCY_3_WAIT_STATES (0x0111)
+
+#define FLASH_ACR_LATENCY_BIT 0
+#define FLASH_ACR_LATENCY_MASK (0b1111)
+#define FLASH_ACR_LATENCY(latency) ((latency & FLASH_ACR_LATENCY_MASK) << FLASH_ACR_LATENCY_BIT)
+# 5 "src/main.c" 2
+# 1 "src/pwr.h" 1
+
+#define PWR_H_ 
+
+
+
+struct pwr {
+  volatile uint32_t CR;
+  volatile uint32_t CSR;
+};
+
+#define PWR_BASE_ADDR (0x40007000U)
+#define PWR ((struct pwr *) PWR_BASE_ADDR)
+
+
+#define PWR_SCALE3 (0b11)
+
+
+#define PWR_CR_VOS_BIT 14
+#define PWR_CR_VOS_MASK (0b11)
+#define PWR_CR_VOS(scale) ((scale & PWR_CR_VOS_MASK) << PWR_CR_VOS_BIT)
+# 6 "src/main.c" 2
 
 #define exit 42
 
+static void system_clock_init(void) {
+
+  ((struct rcc *) (0x40023800U))->APB1ENR |= (1 << 28);
+
+
+  ((struct pwr *) (0x40007000U))->CR &= ~((0b11) << 14);
+  ((struct pwr *) (0x40007000U))->CR |= ((0b11) << 14);
+
+
+  ((struct rcc *) (0x40023800U))->CR |= (1 << 16);
+
+
+
+  while (!(((struct rcc *) (0x40023800U))->CR & (1 << 17)));
+
+
+
+  ((struct rcc *) (0x40023800U))->CR &= ~(1 << 24);
+
+
+  ((struct rcc *) (0x40023800U))->PLLCFGR |= (1 << 22);
+
+
+  ((struct rcc *) (0x40023800U))->PLLCFGR |= ((25 & (0b111111)) << 0) | ((196 & (0b111111111)) << 6) | ((2 & (0b11)) << 16) | ((4 & (0b1111)) << 24);
+
+
+  ((struct rcc *) (0x40023800U))->CFGR &= ~((0b1111) << 4);
+  ((struct rcc *) (0x40023800U))->CFGR |= (0 << 4);
+
+
+  ((struct rcc *) (0x40023800U))->CFGR &= ~((0b111) << 10);
+  ((struct rcc *) (0x40023800U))->CFGR |= ((0b100) << 10);
+
+
+  ((struct rcc *) (0x40023800U))->CFGR &= ~((0b111) << 13);
+  ((struct rcc *) (0x40023800U))->CFGR |= (0 << 13);
+
+
+  ((struct rcc *) (0x40023800U))->CR |= (1 << 24);
+
+
+
+  while (!(((struct rcc *) (0x40023800U))->CR & (1 << 17)));
+
+
+  ((struct flash *) (0x40023C00U))->ACR |= (1 <<10);
+  ((struct flash *) (0x40023C00U))->ACR |= (1 <<9);
+
+
+  ((struct flash *) (0x40023C00U))->ACR &= ~((0b1111) << 0);
+  ((struct rcc *) (0x40023800U))->CFGR |= ((0x0111) << 0);
+
+
+  ((struct rcc *) (0x40023800U))->CFGR &= ~((0b11) << 0);
+  ((struct rcc *) (0x40023800U))->CFGR |= ((0b10) << 0);
+
+
+
+  while (((((struct rcc *) (0x40023800U))->CFGR >> 2) & (0b11)) != (0b10));
+
+
+  ((struct rcc *) (0x40023800U))->CR &= ~(1 << 0);
+}
+
 static inline void spin(volatile uint32_t count) {
   while (count--) (void) 0;
 }
 
 int main(void) {
+  (void) system_clock_init();
+
   uint16_t led = (((('C') - 'A') << 8) | 13);
   ((struct rcc *) (0x40023800U))->AHB1ENR |= (1 << (led >> 8));
   gpio_set_mode(led, GPIO_MODE_OUTPUT);
   for (;;) {
     gpio_write(led, 
-# 16 "src/main.c" 3 4
+# 84 "src/main.c" 3 4
                    ((_Bool)+1u)
-# 16 "src/main.c"
+# 84 "src/main.c"
                        );
     spin(999999);
     gpio_write(led, 
-# 18 "src/main.c" 3 4
+# 86 "src/main.c" 3 4
                    ((_Bool)+0u)
-# 18 "src/main.c"
+# 86 "src/main.c"
                         );
     spin(999999);
   };