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Configure system clock to run at 96Mhz

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This commit is contained in:
Alexander Heldt
2024-07-31 11:57:35 +02:00
parent 0fec3d6a6c
commit d9389b4eb8
9 changed files with 1252 additions and 527 deletions
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16
src/rcc.h
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@@ -44,13 +44,8 @@ struct rcc {
// PLL toggle
#define RCC_CR_PLLON_BIT 24
#define RCC_CR_PLLON_OFF (0 << RCC_CR_PLLON_BIT)
#define RCC_CR_PLLON_ON (1 << RCC_CR_PLLON_BIT)
// HSE clock bypass
#define RCC_CR_HSEBYP_BIT 18
#define RCC_CR_HSEBYP (1 << RCC_CR_HSEBYP_BIT)
// HSE clock ready flag
#define RCC_CR_HSERDY_BIT 17
#define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT)
@@ -59,8 +54,13 @@ struct rcc {
#define RCC_CR_HSEON_BIT 16
#define RCC_CR_HSEON_ON (1 << RCC_CR_HSEON_BIT)
// HSI clock ready flag
#define RCC_CR_HSIRDY_BIT 1
#define RCC_CR_HSIRDY_READY (1 << RCC_CR_HSIRDY_BIT)
// HSI clock enable
#define RCC_CR_HSION_BIT 0
#define RCC_CR_HSION_OFF (0 << RCC_CR_HSION_BIT)
#define RCC_CR_HSION_ON (1 << RCC_CR_HSION_BIT)
// PLLCFGR Register
#define RCC_PLLCFGR_PLLQ_BIT 24 // Bits [27:24]
@@ -114,4 +114,8 @@ struct rcc {
#define RCC_CFGR_SW_MASK (0b11)
#define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT)
// APB1ENR Register
#define RCC_APB1ENR_PWREN_BIT 28
#define RCC_APB1ENR_PWREN_CLOCK_ENABLE (1 << RCC_APB1ENR_PWREN_BIT)
#endif