118 lines
4.2 KiB
C
118 lines
4.2 KiB
C
#ifndef RCC_H_
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#define RCC_H_
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#include <inttypes.h>
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struct rcc {
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volatile uint32_t CR; // Clock control register
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volatile uint32_t PLLCFGR; // PLL configuration register
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volatile uint32_t CFGR; // Clock configuration register
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volatile uint32_t CIR; // Clock interrupt register
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volatile uint32_t AHB1RSTR; // AHB1 peripheral reset register
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volatile uint32_t AHB2RSTR; // AHB2 peripheral reset register
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volatile uint32_t RESERVED0[2]; // Reserved (padding)
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volatile uint32_t APB1RSTR; // APB1 peripheral reset register
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volatile uint32_t APB2RSTR; // APB2 peripheral reset register
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volatile uint32_t RESERVED1[2]; // Reserved (padding)
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volatile uint32_t AHB1ENR; // AHB1 peripheral clock enable register
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volatile uint32_t AHB2ENR; // AHB2 peripheral clock enable register
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volatile uint32_t RESERVED2[2]; // Reserved (padding)
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volatile uint32_t APB1ENR; // APB1 peripheral clock enable register
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volatile uint32_t APB2ENR; // APB2 peripheral clock enable register
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volatile uint32_t RESERVED3[2]; // Reserved (padding)
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volatile uint32_t AHB1LPENR; // AHB1 peripheral clock enable in low power mode register
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volatile uint32_t AHB2LPENR; // AHB2 peripheral clock enable in low power mode register
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volatile uint32_t RESERVED4[2]; // Reserved (padding)
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volatile uint32_t APB1LPENR; // APB1 peripheral clock enable in low power mode register
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volatile uint32_t APB2LPENR; // APB2 peripheral clock enable in low power mode register
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volatile uint32_t RESERVED5[2]; // Reserved (padding)
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volatile uint32_t BDCR; // Backup domain control register
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volatile uint32_t CSR; // Clock control & status register
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volatile uint32_t RESERVED6[2]; // Reserved (padding)
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volatile uint32_t SSCGR; // Spread spectrum clock generation register
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volatile uint32_t PLLI2SCFGR; // PLLI2S configuration register
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volatile uint32_t DCKCFGR; // Dedicated clocks configuration register
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};
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#define RCC_BASE_ADDR (0x40023800U)
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#define RCC ((struct rcc *) RCC_BASE_ADDR)
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// CR Register
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// PLL ready flag
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#define RCC_CR_PLLRDY_BIT 25
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#define RCC_CR_PLLRDY_LOCKED (1 << RCC_CR_PLLRDY_BIT)
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// PLL toggle
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#define RCC_CR_PLLON_BIT 24
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#define RCC_CR_PLLON_OFF (0 << RCC_CR_PLLON_BIT)
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#define RCC_CR_PLLON_ON (1 << RCC_CR_PLLON_BIT)
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// HSE clock bypass
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#define RCC_CR_HSEBYP_BIT 18
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#define RCC_CR_HSEBYP (1 << RCC_CR_HSEBYP_BIT)
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// HSE clock ready flag
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#define RCC_CR_HSERDY_BIT 17
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#define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT)
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// HSE clock enable
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#define RCC_CR_HSEON_BIT 16
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#define RCC_CR_HSEON_ON (1 << RCC_CR_HSEON_BIT)
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#define RCC_CR_HSION_BIT 0
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#define RCC_CR_HSION_OFF (0 << RCC_CR_HSION_BIT)
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// PLLCFGR Register
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#define RCC_PLLCFGR_PLLQ_BIT 24 // Bits [27:24]
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#define RCC_PLLCFGR_PLLQ_MASK (0b1111)
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#define RCC_PLLCFGR_PLLQ(q) ((q & RCC_PLLCFGR_PLLQ_MASK) << RCC_PLLCFGR_PLLQ_BIT)
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#define RCC_PLLCFGR_PLLSRC_BIT 22
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#define RCC_PLLCFGR_PLLSRC_HSE (1 << RCC_PLLCFGR_PLLSRC_BIT)
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#define RCC_PLLCFGR_PLLP_BIT 16 // Bits [17:16]
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#define RCC_PLLCFGR_PLLP_MASK (0b11)
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#define RCC_PLLCFGR_PLLP(p) ((p & RCC_PLLCFGR_PLLP_MASK) << RCC_PLLCFGR_PLLP_BIT)
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#define RCC_PLLCFGR_PLLN_BIT 6 // Bits [14:6]
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#define RCC_PLLCFGR_PLLN_MASK (0b111111111)
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#define RCC_PLLCFGR_PLLN(n) ((n & RCC_PLLCFGR_PLLN_MASK) << RCC_PLLCFGR_PLLN_BIT)
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#define RCC_PLLCFGR_PLLM_BIT 0 // Bits [5:0]
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#define RCC_PLLCFGR_PLLM_MASK (0b111111)
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#define RCC_PLLCFGR_PLLM(m) ((m & RCC_PLLCFGR_PLLM_MASK) << RCC_PLLCFGR_PLLM_BIT)
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// CFGR Register
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// APB{1,2} prescalar
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#define RCC_CFGR_PPRE_DIV_NONE 0
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#define RCC_CFGR_PPRE_DIV_2 (0b100)
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// APB2
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#define RCC_CFGR_PPRE2_BIT 13 // Bits [15:13]
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#define RCC_CFGR_PPRE2_MASK (0b111)
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// APB1
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#define RCC_CFGR_PPRE1_BIT 10 // Bits [12:10]
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#define RCC_CFGR_PPRE1_MASK (0b111)
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// AHB prescalar
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#define RCC_CFGR_HPRE_DIV_NONE 0
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#define RCC_CFGR_HPRE_BIT 4 // Bits [7:4]
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#define RCC_CFGR_HPRE_MASK (0b1111)
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//System clock switch status
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#define RCC_CFGR_SWS_PLL (0b10)
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#define RCC_CFGR_SWS_BIT 2 // Bits [3:2]
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#define RCC_CFGR_SWS_MASK (0b11)
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// System clock switch
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#define RCC_CFGR_SW_PLL (0b10)
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#define RCC_CFGR_SW_BIT 0 // Bits [1:0]
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#define RCC_CFGR_SW_MASK (0b11)
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#define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT)
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#endif
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