Turn off HSI earlier

build/main.S

@@ -61,164 +61,165 @@ system_clock_init:
 	ldr	r3, [r3]
 	ldr	r2, .L5
 	.loc 1 21 38
-	orr	r3, r3, #65536
+	bic	r3, r3, #1
 	str	r3, [r2]
-	.loc 1 25 9
+	.loc 1 24 33
-	nop
-.L2:
-	.loc 1 25 42 discriminator 1
-	ldr	r3, .L5
-	ldr	r3, [r3]
-	.loc 1 25 47 discriminator 1
-	and	r3, r3, #131072
-	.loc 1 25 10 discriminator 1
-	cmp	r3, #0
-	beq	.L2
-	.loc 1 29 33
 	ldr	r3, .L5
 	ldr	r3, [r3]
 	ldr	r2, .L5
-	.loc 1 29 38
+	.loc 1 24 38
+	orr	r3, r3, #65536
+	str	r3, [r2]
+	.loc 1 28 9
+	nop
+.L2:
+	.loc 1 28 42 discriminator 1
+	ldr	r3, .L5
+	ldr	r3, [r3]
+	.loc 1 28 47 discriminator 1
+	and	r3, r3, #131072
+	.loc 1 28 10 discriminator 1
+	cmp	r3, #0
+	beq	.L2
+	.loc 1 32 33
+	ldr	r3, .L5
+	ldr	r3, [r3]
+	ldr	r2, .L5
+	.loc 1 32 38
 	bic	r3, r3, #16777216
 	str	r3, [r2]
-	.loc 1 32 33
+	.loc 1 35 33
 	ldr	r3, .L5
 	ldr	r3, [r3, #4]
 	ldr	r2, .L5
-	.loc 1 32 43
+	.loc 1 35 43
 	orr	r3, r3, #4194304
 	str	r3, [r2, #4]
-	.loc 1 35 33
+	.loc 1 38 33
 	ldr	r3, .L5
 	ldr	r2, [r3, #4]
 	ldr	r1, .L5
-	.loc 1 35 43
+	.loc 1 38 43
 	ldr	r3, .L5+8
 	orrs	r3, r3, r2
 	str	r3, [r1, #4]
-	.loc 1 38 33
+	.loc 1 41 33
 	ldr	r3, .L5
 	ldr	r3, [r3, #8]
 	ldr	r2, .L5
-	.loc 1 38 40
+	.loc 1 41 40
 	bic	r3, r3, #240
 	str	r3, [r2, #8]
-	.loc 1 39 33
-	ldr	r3, .L5
-	ldr	r2, .L5
-	ldr	r3, [r3, #8]
-	.loc 1 39 40
-	str	r3, [r2, #8]
 	.loc 1 42 33
 	ldr	r3, .L5
-	ldr	r3, [r3, #8]
 	ldr	r2, .L5
+	ldr	r3, [r3, #8]
 	.loc 1 42 40
-	bic	r3, r3, #7168
 	str	r3, [r2, #8]
-	.loc 1 43 33
+	.loc 1 45 33
 	ldr	r3, .L5
 	ldr	r3, [r3, #8]
 	ldr	r2, .L5
-	.loc 1 43 40
+	.loc 1 45 40
-	orr	r3, r3, #4096
+	bic	r3, r3, #7168
 	str	r3, [r2, #8]
 	.loc 1 46 33
 	ldr	r3, .L5
 	ldr	r3, [r3, #8]
 	ldr	r2, .L5
 	.loc 1 46 40
-	bic	r3, r3, #57344
+	orr	r3, r3, #4096
 	str	r3, [r2, #8]
-	.loc 1 47 33
+	.loc 1 49 33
 	ldr	r3, .L5
-	ldr	r2, .L5
 	ldr	r3, [r3, #8]
-	.loc 1 47 40
+	ldr	r2, .L5
+	.loc 1 49 40
+	bic	r3, r3, #57344
 	str	r3, [r2, #8]
 	.loc 1 50 33
 	ldr	r3, .L5
-	ldr	r3, [r3]
 	ldr	r2, .L5
-	.loc 1 50 38
+	ldr	r3, [r3, #8]
-	orr	r3, r3, #16777216
+	.loc 1 50 40
-	str	r3, [r2]
+	str	r3, [r2, #8]
-	.loc 1 54 9
+	.loc 1 53 33
-	nop
-.L3:
-	.loc 1 54 42 discriminator 1
 	ldr	r3, .L5
 	ldr	r3, [r3]
-	.loc 1 54 47 discriminator 1
+	ldr	r2, .L5
+	.loc 1 53 38
+	orr	r3, r3, #16777216
+	str	r3, [r2]
+	.loc 1 57 9
+	nop
+.L3:
+	.loc 1 57 42 discriminator 1
+	ldr	r3, .L5
+	ldr	r3, [r3]
+	.loc 1 57 47 discriminator 1
 	and	r3, r3, #33554432
-	.loc 1 54 10 discriminator 1
+	.loc 1 57 10 discriminator 1
 	cmp	r3, #0
 	beq	.L3
-	.loc 1 57 35
+	.loc 1 60 35
 	ldr	r3, .L5+12
 	ldr	r3, [r3]
 	ldr	r2, .L5+12
-	.loc 1 57 41
+	.loc 1 60 41
 	orr	r3, r3, #1024
 	str	r3, [r2]
-	.loc 1 58 35
-	ldr	r3, .L5+12
-	ldr	r3, [r3]
-	ldr	r2, .L5+12
-	.loc 1 58 41
-	orr	r3, r3, #512
-	str	r3, [r2]
 	.loc 1 61 35
 	ldr	r3, .L5+12
 	ldr	r3, [r3]
 	ldr	r2, .L5+12
 	.loc 1 61 41
+	orr	r3, r3, #512
+	str	r3, [r2]
+	.loc 1 64 35
+	ldr	r3, .L5+12
+	ldr	r3, [r3]
+	ldr	r2, .L5+12
+	.loc 1 64 41
 	bic	r3, r3, #15
 	str	r3, [r2]
-	.loc 1 62 33
-	ldr	r3, .L5
-	ldr	r3, [r3, #8]
-	ldr	r2, .L5
-	.loc 1 62 40
-	orr	r3, r3, #272
-	orr	r3, r3, #1
-	str	r3, [r2, #8]
 	.loc 1 65 33
 	ldr	r3, .L5
 	ldr	r3, [r3, #8]
 	ldr	r2, .L5
 	.loc 1 65 40
+	orr	r3, r3, #272
+	orr	r3, r3, #1
+	str	r3, [r2, #8]
+	.loc 1 68 33
+	ldr	r3, .L5
+	ldr	r3, [r3, #8]
+	ldr	r2, .L5
+	.loc 1 68 40
 	bic	r3, r3, #3
 	str	r3, [r2, #8]
-	.loc 1 66 33
+	.loc 1 69 33
 	ldr	r3, .L5
 	ldr	r3, [r3, #8]
 	ldr	r2, .L5
-	.loc 1 66 40
+	.loc 1 69 40
 	orr	r3, r3, #2
 	str	r3, [r2, #8]
-	.loc 1 70 9
+	.loc 1 73 9
 	nop
 .L4:
-	.loc 1 70 42 discriminator 1
+	.loc 1 73 42 discriminator 1
 	ldr	r3, .L5
 	ldr	r3, [r3, #8]
-	.loc 1 70 49 discriminator 1
+	.loc 1 73 49 discriminator 1
 	lsrs	r3, r3, #2
-	.loc 1 70 55 discriminator 1
+	.loc 1 73 55 discriminator 1
 	and	r3, r3, #3
-	.loc 1 70 65 discriminator 1
+	.loc 1 73 65 discriminator 1
 	cmp	r3, #2
 	bne	.L4
-	.loc 1 73 33
-	ldr	r3, .L5
-	ldr	r3, [r3]
-	ldr	r2, .L5
-	.loc 1 73 38
-	bic	r3, r3, #1
-	str	r3, [r2]
 	.loc 1 74 1
 	nop
+	nop
 	mov	sp, r7
 	.cfi_def_cfa_register 13
 	@ sp needed

build/main.i

@@ -2255,6 +2255,9 @@ static void system_clock_init(void) {
   ((struct pwr *) (0x40007000U))->CR |= ((0b11) << 14);
 
 
+  ((struct rcc *) (0x40023800U))->CR &= ~(1 << 0);
+
+
   ((struct rcc *) (0x40023800U))->CR |= (1 << 16);
 
 
@@ -2305,9 +2308,6 @@ static void system_clock_init(void) {
 
 
   while (((((struct rcc *) (0x40023800U))->CFGR >> 2) & (0b11)) != (0b10));
-
-
-  ((struct rcc *) (0x40023800U))->CR &= ~(1 << 0);
 }
 
 int main(void) {

src/main.c

@@ -17,6 +17,9 @@ static void system_clock_init(void) {
   PWR->CR &= ~(PWR_CR_VOS_MASK << PWR_CR_VOS_BIT);
   PWR->CR |= (PWR_SCALE3 << PWR_CR_VOS_BIT);
 
+  // Turn off HSI (which is on by default)
+  RCC->CR &= ~RCC_CR_HSION_ON;
+
   // Turn on HSE
   RCC->CR |= RCC_CR_HSEON_ON;
 
@@ -68,9 +71,6 @@ static void system_clock_init(void) {
   // Wait indefinitely for PLL clock to be selected
   // TODO indicate error/timeout somehow?
   while (((RCC->CFGR >> RCC_CFGR_SWS_BIT) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL);
-
-  // Turn off HSI (which is on by default)
-  RCC->CR &= ~RCC_CR_HSION_ON;
 }
 
 int main(void) {