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Set correct PLL N for 96MHz

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This commit is contained in:
Alexander Heldt
2024-12-30 11:47:18 +01:00
parent a63527a997
commit 916d7d9620
5 changed files with 3 additions and 3 deletions
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build/final.elf
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build/main.S
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@@ -231,7 +231,7 @@ system_clock_init:
.L5:
.word 1073887232
.word 1073770496
.word 67252505
.word 67252249
.word 1073888256
.cfi_endproc
.LFE0:

2
build/main.i
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@@ -2269,7 +2269,7 @@ static void system_clock_init(void) {
((struct rcc *) (0x40023800U))->PLLCFGR |= (1 << 22);
((struct rcc *) (0x40023800U))->PLLCFGR |= ((25 & (0b111111)) << 0) | ((196 & (0b111111111)) << 6) | ((2 & (0b11)) << 16) | ((4 & (0b1111)) << 24);
((struct rcc *) (0x40023800U))->PLLCFGR |= ((25 & (0b111111)) << 0) | ((192 & (0b111111111)) << 6) | ((2 & (0b11)) << 16) | ((4 & (0b1111)) << 24);
((struct rcc *) (0x40023800U))->CFGR &= ~((0b1111) << 4);

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build/main.o
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src/main.c
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@@ -32,7 +32,7 @@ static void system_clock_init(void) {
RCC->PLLCFGR |= RCC_PLLCFGR_PLLSRC_HSE;
// Settings to achieve system clock of 96Mhz
RCC->PLLCFGR |= RCC_PLLCFGR_PLLM(25) | RCC_PLLCFGR_PLLN(196) | RCC_PLLCFGR_PLLP(2) | RCC_PLLCFGR_PLLQ(4);
RCC->PLLCFGR |= RCC_PLLCFGR_PLLM(25) | RCC_PLLCFGR_PLLN(192) | RCC_PLLCFGR_PLLP(2) | RCC_PLLCFGR_PLLQ(4);
// Set AHB prescalar to /1
RCC->CFGR &= ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_BIT);