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Use RCC_CFGR_SW helper function to set software clock

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This commit is contained in:
Alexander Heldt
2024-12-30 11:48:38 +01:00
parent 11f469564f
commit 3aad7271a1
6 changed files with 141 additions and 150 deletions
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build/final.elf
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204
build/final.elf.map
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@@ -121,7 +121,7 @@ LOAD build/timer.o
0x08000000 interrupt_vector_table
0x08000198 . = ALIGN (0x4)
.text 0x08000198 0x358
.text 0x08000198 0x34c
0x08000198 . = ALIGN (0x4)
*(.text)
*(.text.*)
@@ -133,114 +133,114 @@ LOAD build/timer.o
0x080001fa gpio_write
*fill* 0x08000246 0x2
.text.system_clock_init
0x08000248 0x144 build/main.o
.text.main 0x0800038c 0x88 build/main.o
0x0800038c main
0x08000248 0x138 build/main.o
.text.main 0x08000380 0x88 build/main.o
0x08000380 main
.text.init_memory
0x08000414 0x64 build/startup.o
0x08000414 init_memory
.text.reset 0x08000478 0x10 build/startup.o
0x08000478 reset
0x08000408 0x64 build/startup.o
0x08000408 init_memory
.text.reset 0x0800046c 0x10 build/startup.o
0x0800046c reset
.text.default_handler
0x08000488 0x8 build/startup.o
0x08000488 exti0
0x08000488 debug_monitor
0x08000488 rcc
0x08000488 x
0x08000488 sdio
0x08000488 usage_fault
0x08000488 tim1_up_tim10
0x08000488 usart1
0x08000488 i2c3_er
0x08000488 spi2
0x08000488 dma1_stream1
0x08000488 bus_fault
0x08000488 spi5
0x08000488 exti3
0x08000488 dma2_stream5
0x08000488 tim2
0x08000488 dma1_stream6
0x08000488 default_handler
0x08000488 i2c1_er
0x08000488 hard_fault
0x08000488 usart6
0x08000488 exti15_10
0x08000488 usart2
0x08000488 pend_sv
0x08000488 i2c1_ev
0x08000488 wwdg
0x08000488 adc
0x08000488 rtc_alarm
0x08000488 spi3
0x08000488 exti1
0x08000488 mem_manage
0x08000488 dma2_stream1
0x08000488 dma1_stream2
0x08000488 dma2_stream3
0x08000488 sv_call
0x08000488 tim3
0x08000488 otg_fs
0x08000488 dma1_stream5
0x08000488 dma2_stream6
0x08000488 flash
0x08000488 tamp_stamp
0x08000488 i2c3_ev
0x08000488 rtc_wkup
0x08000488 dma2_stream0
0x08000488 pvd
0x08000488 fpu
0x08000488 exti4
0x08000488 exti2
0x08000488 spi1
0x08000488 dma1_stream0
0x08000488 tim1_brk_tim9
0x08000488 i2c2_ev
0x08000488 otg_fs_wkup
0x08000488 spi4
0x08000488 dma2_stream2
0x08000488 tim1_cc
0x08000488 tim1_trg_com_tim11
0x08000488 exti9_5
0x08000488 dma1_stream3
0x08000488 dma2_stream4
0x08000488 i2c2_er
0x08000488 dma2_stream7
0x08000488 dma1_stream7
0x08000488 nmi
0x08000488 systick
0x08000488 tim4
0x08000488 tim5
0x08000488 dma1_stream4
0x0800047c 0x8 build/startup.o
0x0800047c exti0
0x0800047c debug_monitor
0x0800047c rcc
0x0800047c x
0x0800047c sdio
0x0800047c usage_fault
0x0800047c tim1_up_tim10
0x0800047c usart1
0x0800047c i2c3_er
0x0800047c spi2
0x0800047c dma1_stream1
0x0800047c bus_fault
0x0800047c spi5
0x0800047c exti3
0x0800047c dma2_stream5
0x0800047c tim2
0x0800047c dma1_stream6
0x0800047c default_handler
0x0800047c i2c1_er
0x0800047c hard_fault
0x0800047c usart6
0x0800047c exti15_10
0x0800047c usart2
0x0800047c pend_sv
0x0800047c i2c1_ev
0x0800047c wwdg
0x0800047c adc
0x0800047c rtc_alarm
0x0800047c spi3
0x0800047c exti1
0x0800047c mem_manage
0x0800047c dma2_stream1
0x0800047c dma1_stream2
0x0800047c dma2_stream3
0x0800047c sv_call
0x0800047c tim3
0x0800047c otg_fs
0x0800047c dma1_stream5
0x0800047c dma2_stream6
0x0800047c flash
0x0800047c tamp_stamp
0x0800047c i2c3_ev
0x0800047c rtc_wkup
0x0800047c dma2_stream0
0x0800047c pvd
0x0800047c fpu
0x0800047c exti4
0x0800047c exti2
0x0800047c spi1
0x0800047c dma1_stream0
0x0800047c tim1_brk_tim9
0x0800047c i2c2_ev
0x0800047c otg_fs_wkup
0x0800047c spi4
0x0800047c dma2_stream2
0x0800047c tim1_cc
0x0800047c tim1_trg_com_tim11
0x0800047c exti9_5
0x0800047c dma1_stream3
0x0800047c dma2_stream4
0x0800047c i2c2_er
0x0800047c dma2_stream7
0x0800047c dma1_stream7
0x0800047c nmi
0x0800047c systick
0x0800047c tim4
0x0800047c tim5
0x0800047c dma1_stream4
.text.tim4_init
0x08000490 0x40 build/timer.o
0x08000490 tim4_init
0x08000484 0x40 build/timer.o
0x08000484 tim4_init
.text.tim4_start
0x080004d0 0x20 build/timer.o
0x080004d0 tim4_start
0x080004c4 0x20 build/timer.o
0x080004c4 tim4_start
*(.rodata)
*(.rodata.*)
0x080004f0 . = ALIGN (0x4)
0x080004f0 _data_addr = LOADADDR (.data)
0x080004e4 . = ALIGN (0x4)
0x080004e4 _data_addr = LOADADDR (.data)
.glue_7 0x080004f0 0x0
.glue_7 0x080004f0 0x0 linker stubs
.glue_7 0x080004e4 0x0
.glue_7 0x080004e4 0x0 linker stubs
.glue_7t 0x080004f0 0x0
.glue_7t 0x080004f0 0x0 linker stubs
.glue_7t 0x080004e4 0x0
.glue_7t 0x080004e4 0x0 linker stubs
.vfp11_veneer 0x080004f0 0x0
.vfp11_veneer 0x080004f0 0x0 linker stubs
.vfp11_veneer 0x080004e4 0x0
.vfp11_veneer 0x080004e4 0x0 linker stubs
.v4_bx 0x080004f0 0x0
.v4_bx 0x080004f0 0x0 linker stubs
.v4_bx 0x080004e4 0x0
.v4_bx 0x080004e4 0x0 linker stubs
.iplt 0x080004f0 0x0
.iplt 0x080004f0 0x0 build/main.o
.iplt 0x080004e4 0x0
.iplt 0x080004e4 0x0 build/main.o
.rel.dyn 0x080004f0 0x0
.rel.iplt 0x080004f0 0x0 build/main.o
.rel.dyn 0x080004e4 0x0
.rel.iplt 0x080004e4 0x0 build/main.o
.data 0x20000000 0x0 load address 0x080004f0
.data 0x20000000 0x0 load address 0x080004e4
0x20000000 . = ALIGN (0x4)
0x20000000 _data_start = .
*(.data)
@@ -248,10 +248,10 @@ LOAD build/timer.o
0x20000000 . = ALIGN (0x4)
0x20000000 _data_end = .
.igot.plt 0x20000000 0x0 load address 0x080004f0
.igot.plt 0x20000000 0x0 load address 0x080004e4
.igot.plt 0x20000000 0x0 build/main.o
.bss 0x20000000 0x0 load address 0x080004f0
.bss 0x20000000 0x0 load address 0x080004e4
0x20000000 . = ALIGN (0x4)
0x20000000 _bss_start = .
*(.bss)
@@ -321,11 +321,11 @@ LOAD linker stubs
.debug_macro 0x00002f20 0xb5c build/timer.o
.debug_macro 0x00003a7c 0x124 build/timer.o
.debug_line 0x00000000 0x4b9
.debug_line 0x00000000 0x4b3
.debug_line 0x00000000 0x116 build/gpio.o
.debug_line 0x00000116 0x1da build/main.o
.debug_line 0x000002f0 0xea build/startup.o
.debug_line 0x000003da 0xdf build/timer.o
.debug_line 0x00000116 0x1d4 build/main.o
.debug_line 0x000002ea 0xea build/startup.o
.debug_line 0x000003d4 0xdf build/timer.o
.debug_str 0x00000000 0x5eb4
.debug_str 0x00000000 0x536f build/gpio.o

73
build/main.S
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@@ -195,29 +195,22 @@ system_clock_init:
ldr r3, [r3, #8]
ldr r2, .L5
.loc 1 68 40
bic r3, r3, #3
str r3, [r2, #8]
.loc 1 69 33
ldr r3, .L5
ldr r3, [r3, #8]
ldr r2, .L5
.loc 1 69 40
orr r3, r3, #2
str r3, [r2, #8]
.loc 1 73 9
.loc 1 72 9
nop
.L4:
.loc 1 73 42 discriminator 1
.loc 1 72 42 discriminator 1
ldr r3, .L5
ldr r3, [r3, #8]
.loc 1 73 49 discriminator 1
.loc 1 72 49 discriminator 1
lsrs r3, r3, #2
.loc 1 73 55 discriminator 1
.loc 1 72 55 discriminator 1
and r3, r3, #3
.loc 1 73 65 discriminator 1
.loc 1 72 65 discriminator 1
cmp r3, #2
bne .L4
.loc 1 74 1
.loc 1 73 1
nop
nop
mov sp, r7
@@ -246,7 +239,7 @@ system_clock_init:
.type main, %function
main:
.LFB1:
.loc 1 76 16
.loc 1 75 16
.cfi_startproc
@ args = 0, pretend = 0, frame = 8
@ frame_needed = 1, uses_anonymous_args = 0
@@ -258,56 +251,56 @@ main:
.cfi_def_cfa_offset 16
add r7, sp, #0
.cfi_def_cfa_register 7
.loc 1 77 3
.loc 1 76 3
bl system_clock_init
.loc 1 78 3
.loc 1 77 3
bl tim4_init
.loc 1 80 3
.loc 1 79 3
bl tim4_start
.loc 1 82 12
.loc 1 81 12
movw r3, #525
strh r3, [r7, #2] @ movhi
.loc 1 83 33
.loc 1 82 33
ldr r3, .L10
ldr r3, [r3, #48]
.loc 1 83 57
.loc 1 82 57
ldrh r2, [r7, #2]
lsrs r2, r2, #8
uxth r2, r2
mov r1, r2
.loc 1 83 49
.loc 1 82 49
movs r2, #1
lsls r2, r2, r1
mov r1, r2
.loc 1 83 33
.loc 1 82 33
ldr r2, .L10
.loc 1 83 43
.loc 1 82 43
orrs r3, r3, r1
str r3, [r2, #48]
.loc 1 84 3
.loc 1 83 3
ldrh r3, [r7, #2]
movs r1, #1
mov r0, r3
bl gpio_set_mode
.loc 1 86 54
.loc 1 85 54
ldr r3, .L10+4
ldr r3, [r3, #36]
.loc 1 86 12
.loc 1 85 12
strh r3, [r7, #6] @ movhi
.loc 1 87 7
.loc 1 86 7
movs r3, #0
strb r3, [r7, #5]
.L9:
.loc 1 89 39
.loc 1 88 39
ldr r3, .L10+4
ldr r2, [r3, #36]
.loc 1 89 45
.loc 1 88 45
ldrh r3, [r7, #6]
subs r3, r2, r3
.loc 1 89 5
.loc 1 88 5
cmp r3, #249
bls .L9
.loc 1 90 3
.loc 1 89 3
ldrb r3, [r7, #5] @ zero_extendqisi2
cmp r3, #0
ite ne
@@ -316,23 +309,23 @@ main:
uxtb r3, r3
eor r3, r3, #1
uxtb r3, r3
.loc 1 90 10
.loc 1 89 10
strb r3, [r7, #5]
ldrb r3, [r7, #5]
and r3, r3, #1
strb r3, [r7, #5]
.loc 1 91 3
.loc 1 90 3
ldrb r2, [r7, #5] @ zero_extendqisi2
ldrh r3, [r7, #2]
mov r1, r2
mov r0, r3
bl gpio_write
.loc 1 93 45
.loc 1 92 45
ldr r3, .L10+4
ldr r3, [r3, #36]
.loc 1 93 11
.loc 1 92 11
strh r3, [r7, #6] @ movhi
.loc 1 89 5
.loc 1 88 5
b .L9
.L11:
.align 2
@@ -860,7 +853,7 @@ main:
.uleb128 0x12
.4byte .LASF1005
.byte 0x1
.byte 0x4c
.byte 0x4b
.byte 0x5
.4byte 0x7a
.4byte .LFB1
@@ -871,7 +864,7 @@ main:
.uleb128 0x13
.ascii "led\000"
.byte 0x1
.byte 0x52
.byte 0x51
.byte 0xc
.4byte 0x88
.uleb128 0x2
@@ -879,7 +872,7 @@ main:
.sleb128 -14
.uleb128 0xc
.4byte .LASF1000
.byte 0x56
.byte 0x55
.byte 0xc
.4byte 0x88
.uleb128 0x2
@@ -887,7 +880,7 @@ main:
.sleb128 -10
.uleb128 0xc
.4byte .LASF1001
.byte 0x57
.byte 0x56
.byte 0x7
.4byte 0x3cd
.uleb128 0x2

11
build/main.i
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@@ -2302,8 +2302,7 @@ static void system_clock_init(void) {
((struct rcc *) (0x40023800U))->CFGR |= ((0x0111) << 0);
((struct rcc *) (0x40023800U))->CFGR &= ~((0b11) << 0);
((struct rcc *) (0x40023800U))->CFGR |= ((0b10) << 0);
((struct rcc *) (0x40023800U))->CFGR |= (((0b10) & (0b11)) << 0);
@@ -2322,13 +2321,13 @@ int main(void) {
uint16_t counter = ((struct timer *) (0x40000800U))->CNT;
# 87 "src/main.c" 3 4
# 86 "src/main.c" 3 4
_Bool
# 87 "src/main.c"
# 86 "src/main.c"
led_on =
# 87 "src/main.c" 3 4
# 86 "src/main.c" 3 4
((_Bool)+0u)
# 87 "src/main.c"
# 86 "src/main.c"
;
while(1) {
if ((((struct timer *) (0x40000800U))->CNT - counter) >= 250) {

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build/main.o
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3
src/main.c
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@@ -65,8 +65,7 @@ static void system_clock_init(void) {
RCC->CFGR |= (FLASH_ACR_LATENCY_3_WAIT_STATES << FLASH_ACR_LATENCY_BIT);
// Use PLL as system clock
RCC->CFGR &= ~(RCC_CFGR_SW_MASK << RCC_CFGR_SW_BIT);
RCC->CFGR |= (RCC_CFGR_SW_PLL << RCC_CFGR_SW_BIT);
RCC->CFGR |= RCC_CFGR_SW(RCC_CFGR_SW_PLL);
// Wait indefinitely for PLL clock to be selected
// TODO indicate error/timeout somehow?