Set correct PLL N for 96MHz
This commit is contained in:
@@ -32,7 +32,7 @@ static void system_clock_init(void) {
|
|||||||
RCC->PLLCFGR |= RCC_PLLCFGR_PLLSRC_HSE;
|
RCC->PLLCFGR |= RCC_PLLCFGR_PLLSRC_HSE;
|
||||||
|
|
||||||
// Settings to achieve system clock of 96Mhz
|
// Settings to achieve system clock of 96Mhz
|
||||||
RCC->PLLCFGR |= RCC_PLLCFGR_PLLM(25) | RCC_PLLCFGR_PLLN(196) | RCC_PLLCFGR_PLLP(2) | RCC_PLLCFGR_PLLQ(4);
|
RCC->PLLCFGR |= RCC_PLLCFGR_PLLM(25) | RCC_PLLCFGR_PLLN(192) | RCC_PLLCFGR_PLLP(2) | RCC_PLLCFGR_PLLQ(4);
|
||||||
|
|
||||||
// Set AHB prescalar to /1
|
// Set AHB prescalar to /1
|
||||||
RCC->CFGR &= ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_BIT);
|
RCC->CFGR &= ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_BIT);
|
||||||
|
|||||||
Reference in New Issue
Block a user