Set correct PLL N for 96MHz
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@@ -32,7 +32,7 @@ static void system_clock_init(void) {
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RCC->PLLCFGR |= RCC_PLLCFGR_PLLSRC_HSE;
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// Settings to achieve system clock of 96Mhz
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RCC->PLLCFGR |= RCC_PLLCFGR_PLLM(25) | RCC_PLLCFGR_PLLN(196) | RCC_PLLCFGR_PLLP(2) | RCC_PLLCFGR_PLLQ(4);
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RCC->PLLCFGR |= RCC_PLLCFGR_PLLM(25) | RCC_PLLCFGR_PLLN(192) | RCC_PLLCFGR_PLLP(2) | RCC_PLLCFGR_PLLQ(4);
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// Set AHB prescalar to /1
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RCC->CFGR &= ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_BIT);
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