wip

Makefile

@@ -31,7 +31,7 @@ ASM_FILES := $(patsubst $(BUILD_DIR)/%.i,$(BUILD_DIR)/%.S,$(PREP_FILES))
 OBJ_FILES := $(patsubst $(BUILD_DIR)/%.S,$(BUILD_DIR)/%.o,$(ASM_FILES))
 
 .PHONY: build
-build: builddir preprocess compile assemble $(BUILD_DIR)/$(TARGET).elf
+build: clean builddir preprocess compile assemble $(BUILD_DIR)/$(TARGET).elf
 
 $(BUILD_DIR)/$(TARGET).bin: $(BUILD_DIR)/$(TARGET).elf
 	arm-none-eabi-objcopy -O binary $< $@
@@ -65,6 +65,18 @@ assemble: compile $(OBJ_FILES)
 flash: $(BUILD_DIR)/$(TARGET).bin
 	st-flash --reset write $< 0x8000000
 
+.PHONY: gdb-server
+gdb-server:
+	sudo openocd -f stlink.cfg -f stm32f4x.cfg
+
+.PHONY: gdb-client
+gdb-client:
+	gdb --symbols $(BUILD_DIR)/$(TARGET).elf --init-eval-command="target extended-remote localhost:3333"
+
+.PHONY: gdb-guiclient
+gdb-guiclient:
+	gdbgui --gdb-cmd="gdb --init-eval-command='target extended-remote localhost:3333'" $(BUILD_DIR)/$(TARGET).elf
+
 .PHONY: clean
 clean:
 	rm -rf $(BUILD_DIR)

build/final.elf.map

@@ -33,6 +33,10 @@ Discarded input sections
  .group         0x00000000        0xc build/main.o
  .group         0x00000000        0xc build/main.o
  .group         0x00000000        0xc build/main.o
+ .group         0x00000000        0xc build/main.o
+ .group         0x00000000        0xc build/main.o
+ .group         0x00000000        0xc build/main.o
+ .group         0x00000000        0xc build/main.o
  .text          0x00000000        0x0 build/main.o
  .data          0x00000000        0x0 build/main.o
  .bss           0x00000000        0x0 build/main.o
@@ -49,6 +53,7 @@ Discarded input sections
  .debug_macro   0x00000000       0x89 build/main.o
  .debug_macro   0x00000000      0x4cc build/main.o
  .debug_macro   0x00000000       0x22 build/main.o
+ .debug_macro   0x00000000       0x88 build/main.o
  .group         0x00000000        0xc build/startup.o
  .group         0x00000000        0xc build/startup.o
  .group         0x00000000        0xc build/startup.o
@@ -62,6 +67,70 @@ Discarded input sections
  .debug_macro   0x00000000      0x103 build/startup.o
  .debug_macro   0x00000000       0x6a build/startup.o
  .debug_macro   0x00000000      0x1df build/startup.o
+ .group         0x00000000        0xc build/timer.o
+ .group         0x00000000        0xc build/timer.o
+ .group         0x00000000        0xc build/timer.o
+ .group         0x00000000        0xc build/timer.o
+ .group         0x00000000        0xc build/timer.o
+ .group         0x00000000        0xc build/timer.o
+ .group         0x00000000        0xc build/timer.o
+ .group         0x00000000        0xc build/timer.o
+ .group         0x00000000        0xc build/timer.o
+ .group         0x00000000        0xc build/timer.o
+ .group         0x00000000        0xc build/timer.o
+ .group         0x00000000        0xc build/timer.o
+ .group         0x00000000        0xc build/timer.o
+ .group         0x00000000        0xc build/timer.o
+ .text          0x00000000        0x0 build/timer.o
+ .data          0x00000000        0x0 build/timer.o
+ .bss           0x00000000        0x0 build/timer.o
+ .debug_macro   0x00000000       0x22 build/timer.o
+ .debug_macro   0x00000000       0x75 build/timer.o
+ .debug_macro   0x00000000       0x2a build/timer.o
+ .debug_macro   0x00000000       0x5c build/timer.o
+ .debug_macro   0x00000000       0x3c build/timer.o
+ .debug_macro   0x00000000      0x103 build/timer.o
+ .debug_macro   0x00000000       0x3a build/timer.o
+ .debug_macro   0x00000000       0x57 build/timer.o
+ .debug_macro   0x00000000       0x6a build/timer.o
+ .debug_macro   0x00000000      0x1df build/timer.o
+ .debug_macro   0x00000000       0x89 build/timer.o
+ .debug_macro   0x00000000      0x4cc build/timer.o
+ .debug_macro   0x00000000       0x22 build/timer.o
+ .group         0x00000000        0xc build/usart.o
+ .group         0x00000000        0xc build/usart.o
+ .group         0x00000000        0xc build/usart.o
+ .group         0x00000000        0xc build/usart.o
+ .group         0x00000000        0xc build/usart.o
+ .group         0x00000000        0xc build/usart.o
+ .group         0x00000000        0xc build/usart.o
+ .group         0x00000000        0xc build/usart.o
+ .group         0x00000000        0xc build/usart.o
+ .group         0x00000000        0xc build/usart.o
+ .group         0x00000000        0xc build/usart.o
+ .group         0x00000000        0xc build/usart.o
+ .group         0x00000000        0xc build/usart.o
+ .group         0x00000000        0xc build/usart.o
+ .group         0x00000000        0xc build/usart.o
+ .group         0x00000000        0xc build/usart.o
+ .text          0x00000000        0x0 build/usart.o
+ .data          0x00000000        0x0 build/usart.o
+ .bss           0x00000000        0x0 build/usart.o
+ .debug_macro   0x00000000       0x22 build/usart.o
+ .debug_macro   0x00000000       0x75 build/usart.o
+ .debug_macro   0x00000000       0x2a build/usart.o
+ .debug_macro   0x00000000       0x5c build/usart.o
+ .debug_macro   0x00000000       0x3c build/usart.o
+ .debug_macro   0x00000000      0x103 build/usart.o
+ .debug_macro   0x00000000       0x3a build/usart.o
+ .debug_macro   0x00000000       0x57 build/usart.o
+ .debug_macro   0x00000000       0x6a build/usart.o
+ .debug_macro   0x00000000      0x1df build/usart.o
+ .debug_macro   0x00000000       0x89 build/usart.o
+ .debug_macro   0x00000000      0x4cc build/usart.o
+ .debug_macro   0x00000000      0x13e build/usart.o
+ .debug_macro   0x00000000       0x22 build/usart.o
+ .debug_macro   0x00000000       0x76 build/usart.o
 
 Memory Configuration
 
@@ -77,6 +146,8 @@ LOAD /nix/store/yr89i11mszv2az19r26l372zgaiivj1c-gcc-arm-embedded-12.3.rel1/bin/
 LOAD build/gpio.o
 LOAD build/main.o
 LOAD build/startup.o
+LOAD build/timer.o
+LOAD build/usart.o
                 0x20020000                        stack_start = (ORIGIN (sram) + LENGTH (sram))
 
 .isr_vector     0x08000000      0x198
@@ -86,7 +157,7 @@ LOAD build/startup.o
                 0x08000000                interrupt_vector_table
                 0x08000198                        . = ALIGN (0x4)
 
-.text           0x08000198      0x1a8
+.text           0x08000198      0x4b0
                 0x08000198                        . = ALIGN (0x4)
  *(.text)
  *(.text.*)
@@ -96,108 +167,125 @@ LOAD build/startup.o
  .text.gpio_write
                 0x080001fa       0x4c build/gpio.o
                 0x080001fa                gpio_write
- .text.spin     0x08000246       0x22 build/main.o
+ *fill*         0x08000246        0x2 
- .text.main     0x08000268       0x5c build/main.o
+ .text.system_clock_init
-                0x08000268                main
+                0x08000248      0x144 build/main.o
+ .text.main     0x0800038c       0x98 build/main.o
+                0x0800038c                main
  .text.init_memory
-                0x080002c4       0x64 build/startup.o
+                0x08000424       0x64 build/startup.o
-                0x080002c4                init_memory
+                0x08000424                init_memory
- .text.reset    0x08000328       0x10 build/startup.o
+ .text.reset    0x08000488       0x10 build/startup.o
-                0x08000328                reset
+                0x08000488                reset
  .text.default_handler
-                0x08000338        0x8 build/startup.o
+                0x08000498        0x8 build/startup.o
-                0x08000338                exti0
+                0x08000498                exti0
-                0x08000338                debug_monitor
+                0x08000498                debug_monitor
-                0x08000338                rcc
+                0x08000498                rcc
-                0x08000338                x
+                0x08000498                x
-                0x08000338                sdio
+                0x08000498                sdio
-                0x08000338                usage_fault
+                0x08000498                usage_fault
-                0x08000338                tim1_up_tim10
+                0x08000498                tim1_up_tim10
-                0x08000338                usart1
+                0x08000498                usart1
-                0x08000338                i2c3_er
+                0x08000498                i2c3_er
-                0x08000338                spi2
+                0x08000498                spi2
-                0x08000338                dma1_stream1
+                0x08000498                dma1_stream1
-                0x08000338                bus_fault
+                0x08000498                bus_fault
-                0x08000338                spi5
+                0x08000498                spi5
-                0x08000338                exti3
+                0x08000498                exti3
-                0x08000338                dma2_stream5
+                0x08000498                dma2_stream5
-                0x08000338                tim2
+                0x08000498                tim2
-                0x08000338                dma1_stream6
+                0x08000498                dma1_stream6
-                0x08000338                default_handler
+                0x08000498                default_handler
-                0x08000338                i2c1_er
+                0x08000498                i2c1_er
-                0x08000338                hard_fault
+                0x08000498                hard_fault
-                0x08000338                usart6
+                0x08000498                usart6
-                0x08000338                exti15_10
+                0x08000498                exti15_10
-                0x08000338                usart2
+                0x08000498                usart2
-                0x08000338                pend_sv
+                0x08000498                pend_sv
-                0x08000338                i2c1_ev
+                0x08000498                i2c1_ev
-                0x08000338                wwdg
+                0x08000498                wwdg
-                0x08000338                adc
+                0x08000498                adc
-                0x08000338                rtc_alarm
+                0x08000498                rtc_alarm
-                0x08000338                spi3
+                0x08000498                spi3
-                0x08000338                exti1
+                0x08000498                exti1
-                0x08000338                mem_manage
+                0x08000498                mem_manage
-                0x08000338                dma2_stream1
+                0x08000498                dma2_stream1
-                0x08000338                dma1_stream2
+                0x08000498                dma1_stream2
-                0x08000338                dma2_stream3
+                0x08000498                dma2_stream3
-                0x08000338                sv_call
+                0x08000498                sv_call
-                0x08000338                tim3
+                0x08000498                tim3
-                0x08000338                otg_fs
+                0x08000498                otg_fs
-                0x08000338                dma1_stream5
+                0x08000498                dma1_stream5
-                0x08000338                dma2_stream6
+                0x08000498                dma2_stream6
-                0x08000338                flash
+                0x08000498                flash
-                0x08000338                tamp_stamp
+                0x08000498                tamp_stamp
-                0x08000338                i2c3_ev
+                0x08000498                i2c3_ev
-                0x08000338                rtc_wkup
+                0x08000498                rtc_wkup
-                0x08000338                dma2_stream0
+                0x08000498                dma2_stream0
-                0x08000338                pvd
+                0x08000498                pvd
-                0x08000338                fpu
+                0x08000498                fpu
-                0x08000338                exti4
+                0x08000498                exti4
-                0x08000338                exti2
+                0x08000498                exti2
-                0x08000338                spi1
+                0x08000498                spi1
-                0x08000338                dma1_stream0
+                0x08000498                dma1_stream0
-                0x08000338                tim1_brk_tim9
+                0x08000498                tim1_brk_tim9
-                0x08000338                i2c2_ev
+                0x08000498                i2c2_ev
-                0x08000338                otg_fs_wkup
+                0x08000498                otg_fs_wkup
-                0x08000338                spi4
+                0x08000498                spi4
-                0x08000338                dma2_stream2
+                0x08000498                dma2_stream2
-                0x08000338                tim1_cc
+                0x08000498                tim1_cc
-                0x08000338                tim1_trg_com_tim11
+                0x08000498                tim1_trg_com_tim11
-                0x08000338                exti9_5
+                0x08000498                exti9_5
-                0x08000338                dma1_stream3
+                0x08000498                dma1_stream3
-                0x08000338                dma2_stream4
+                0x08000498                dma2_stream4
-                0x08000338                i2c2_er
+                0x08000498                i2c2_er
-                0x08000338                dma2_stream7
+                0x08000498                dma2_stream7
-                0x08000338                dma1_stream7
+                0x08000498                dma1_stream7
-                0x08000338                nmi
+                0x08000498                nmi
-                0x08000338                systick
+                0x08000498                systick
-                0x08000338                tim4
+                0x08000498                tim4
-                0x08000338                tim5
+                0x08000498                tim5
-                0x08000338                dma1_stream4
+                0x08000498                dma1_stream4
+ .text.tim4_init
+                0x080004a0       0x40 build/timer.o
+                0x080004a0                tim4_init
+ .text.tim4_start
+                0x080004e0       0x20 build/timer.o
+                0x080004e0                tim4_start
+ .text.usart2_init
+                0x08000500       0xf8 build/usart.o
+                0x08000500                usart2_init
+ .text.usart2_start
+                0x080005f8       0x20 build/usart.o
+                0x080005f8                usart2_start
+ .text.usart2_write_byte
+                0x08000618       0x30 build/usart.o
+                0x08000618                usart2_write_byte
  *(.rodata)
  *(.rodata.*)
-                0x08000340                        . = ALIGN (0x4)
+                0x08000648                        . = ALIGN (0x4)
-                0x08000340                        _data_addr = LOADADDR (.data)
+                0x08000648                        _data_addr = LOADADDR (.data)
 
-.glue_7         0x08000340        0x0
+.glue_7         0x08000648        0x0
- .glue_7        0x08000340        0x0 linker stubs
+ .glue_7        0x08000648        0x0 linker stubs
 
-.glue_7t        0x08000340        0x0
+.glue_7t        0x08000648        0x0
- .glue_7t       0x08000340        0x0 linker stubs
+ .glue_7t       0x08000648        0x0 linker stubs
 
-.vfp11_veneer   0x08000340        0x0
+.vfp11_veneer   0x08000648        0x0
- .vfp11_veneer  0x08000340        0x0 linker stubs
+ .vfp11_veneer  0x08000648        0x0 linker stubs
 
-.v4_bx          0x08000340        0x0
+.v4_bx          0x08000648        0x0
- .v4_bx         0x08000340        0x0 linker stubs
+ .v4_bx         0x08000648        0x0 linker stubs
 
-.iplt           0x08000340        0x0
+.iplt           0x08000648        0x0
- .iplt          0x08000340        0x0 build/main.o
+ .iplt          0x08000648        0x0 build/main.o
 
-.rel.dyn        0x08000340        0x0
+.rel.dyn        0x08000648        0x0
- .rel.iplt      0x08000340        0x0 build/main.o
+ .rel.iplt      0x08000648        0x0 build/main.o
 
-.data           0x20000000        0x0 load address 0x08000340
+.data           0x20000000        0x0 load address 0x08000648
                 0x20000000                        . = ALIGN (0x4)
                 0x20000000                        _data_start = .
  *(.data)
@@ -205,10 +293,10 @@ LOAD build/startup.o
                 0x20000000                        . = ALIGN (0x4)
                 0x20000000                        _data_end = .
 
-.igot.plt       0x20000000        0x0 load address 0x08000340
+.igot.plt       0x20000000        0x0 load address 0x08000648
  .igot.plt      0x20000000        0x0 build/main.o
 
-.bss            0x20000000        0x0 load address 0x08000340
+.bss            0x20000000        0x0 load address 0x08000648
                 0x20000000                        . = ALIGN (0x4)
                 0x20000000                        _bss_start = .
  *(.bss)
@@ -218,34 +306,46 @@ LOAD build/startup.o
 OUTPUT(build/final.elf elf32-littlearm)
 LOAD linker stubs
 
-.debug_info     0x00000000      0x64e
+.debug_info     0x00000000      0xe69
- .debug_info    0x00000000      0x21a build/gpio.o
+ .debug_info    0x00000000      0x205 build/gpio.o
- .debug_info    0x0000021a      0x2ac build/main.o
+ .debug_info    0x00000205      0x478 build/main.o
- .debug_info    0x000004c6      0x188 build/startup.o
+ .debug_info    0x0000067d      0x188 build/startup.o
+ .debug_info    0x00000805      0x335 build/timer.o
+ .debug_info    0x00000b3a      0x32f build/usart.o
 
-.debug_abbrev   0x00000000      0x36d
+.debug_abbrev   0x00000000      0x519
- .debug_abbrev  0x00000000      0x12b build/gpio.o
+ .debug_abbrev  0x00000000      0x119 build/gpio.o
- .debug_abbrev  0x0000012b      0x11b build/main.o
+ .debug_abbrev  0x00000119      0x142 build/main.o
- .debug_abbrev  0x00000246      0x127 build/startup.o
+ .debug_abbrev  0x0000025b      0x127 build/startup.o
+ .debug_abbrev  0x00000382       0xb5 build/timer.o
+ .debug_abbrev  0x00000437       0xe2 build/usart.o
 
-.debug_aranges  0x00000000       0x80
+.debug_aranges  0x00000000       0xd8
  .debug_aranges
                 0x00000000       0x28 build/gpio.o
  .debug_aranges
                 0x00000028       0x28 build/main.o
  .debug_aranges
                 0x00000050       0x30 build/startup.o
+ .debug_aranges
+                0x00000080       0x28 build/timer.o
+ .debug_aranges
+                0x000000a8       0x30 build/usart.o
 
 .debug_rnglists
-                0x00000000       0x51
+                0x00000000       0x8c
  .debug_rnglists
                 0x00000000       0x19 build/gpio.o
  .debug_rnglists
-                0x00000019       0x19 build/main.o
+                0x00000019       0x1b build/main.o
  .debug_rnglists
-                0x00000032       0x1f build/startup.o
+                0x00000034       0x1f build/startup.o
+ .debug_rnglists
+                0x00000053       0x19 build/timer.o
+ .debug_rnglists
+                0x0000006c       0x20 build/usart.o
 
-.debug_macro    0x00000000     0x2d8f
+.debug_macro    0x00000000     0x489d
  .debug_macro   0x00000000      0xb56 build/gpio.o
  .debug_macro   0x00000b56       0x22 build/gpio.o
  .debug_macro   0x00000b78       0x75 build/gpio.o
@@ -260,32 +360,47 @@ LOAD linker stubs
  .debug_macro   0x0000108c       0x89 build/gpio.o
  .debug_macro   0x00001115      0x4cc build/gpio.o
  .debug_macro   0x000015e1       0x22 build/gpio.o
- .debug_macro   0x00001603       0x34 build/gpio.o
+ .debug_macro   0x00001603       0x88 build/gpio.o
- .debug_macro   0x00001637      0xb6b build/main.o
+ .debug_macro   0x0000168b      0xb89 build/main.o
- .debug_macro   0x000021a2       0x16 build/main.o
+ .debug_macro   0x00002214      0x144 build/main.o
- .debug_macro   0x000021b8       0x2e build/main.o
+ .debug_macro   0x00002358       0x46 build/main.o
- .debug_macro   0x000021e6      0xb02 build/startup.o
+ .debug_macro   0x0000239e       0x2e build/main.o
- .debug_macro   0x00002ce8       0x56 build/startup.o
+ .debug_macro   0x000023cc       0x22 build/main.o
- .debug_macro   0x00002d3e       0x51 build/startup.o
+ .debug_macro   0x000023ee       0x76 build/main.o
+ .debug_macro   0x00002464      0xb02 build/startup.o
+ .debug_macro   0x00002f66       0x56 build/startup.o
+ .debug_macro   0x00002fbc       0x51 build/startup.o
+ .debug_macro   0x0000300d      0xb5c build/timer.o
+ .debug_macro   0x00003b69      0x13e build/timer.o
+ .debug_macro   0x00003ca7      0xb74 build/usart.o
+ .debug_macro   0x0000481b       0x82 build/usart.o
 
-.debug_line     0x00000000      0x2fe
+.debug_line     0x00000000      0x63b
  .debug_line    0x00000000      0x116 build/gpio.o
- .debug_line    0x00000116       0xfe build/main.o
+ .debug_line    0x00000116      0x1e4 build/main.o
- .debug_line    0x00000214       0xea build/startup.o
+ .debug_line    0x000002fa       0xea build/startup.o
+ .debug_line    0x000003e4       0xdf build/timer.o
+ .debug_line    0x000004c3      0x178 build/usart.o
 
-.debug_str      0x00000000     0x553c
+.debug_str      0x00000000     0x6393
- .debug_str     0x00000000     0x5372 build/gpio.o
+ .debug_str     0x00000000     0x550b build/gpio.o
-                               0x551a (size before relaxing)
+                               0x56b3 (size before relaxing)
- .debug_str     0x00005372      0x142 build/main.o
+ .debug_str     0x0000550b      0xddd build/main.o
-                               0x5607 (size before relaxing)
+                               0x6440 (size before relaxing)
- .debug_str     0x000054b4       0x88 build/startup.o
+ .debug_str     0x000062e8       0x88 build/startup.o
                                0x3cdf (size before relaxing)
+ .debug_str     0x00006370        0xc build/timer.o
+                               0x5bc5 (size before relaxing)
+ .debug_str     0x0000637c       0x17 build/usart.o
+                               0x6091 (size before relaxing)
 
 .comment        0x00000000       0x45
  .comment       0x00000000       0x45 build/gpio.o
                                  0x46 (size before relaxing)
  .comment       0x00000045       0x46 build/main.o
  .comment       0x00000045       0x46 build/startup.o
+ .comment       0x00000045       0x46 build/timer.o
+ .comment       0x00000045       0x46 build/usart.o
 
 .ARM.attributes
                 0x00000000       0x34
@@ -295,20 +410,32 @@ LOAD linker stubs
                 0x00000034       0x34 build/main.o
  .ARM.attributes
                 0x00000068       0x34 build/startup.o
+ .ARM.attributes
+                0x0000009c       0x34 build/timer.o
+ .ARM.attributes
+                0x000000d0       0x34 build/usart.o
 
 .debug_line_str
-                0x00000000      0x265
+                0x00000000      0x293
  .debug_line_str
                 0x00000000      0x24e build/gpio.o
                                 0x260 (size before relaxing)
  .debug_line_str
-                0x0000024e        0xd build/main.o
+                0x0000024e       0x2b build/main.o
-                                0x266 (size before relaxing)
+                                0x284 (size before relaxing)
  .debug_line_str
-                0x0000025b        0xa build/startup.o
+                0x00000279        0xa build/startup.o
                                 0x21b (size before relaxing)
+ .debug_line_str
+                0x00000283        0x8 build/timer.o
+                                0x25e (size before relaxing)
+ .debug_line_str
+                0x0000028b        0x8 build/usart.o
+                                0x26f (size before relaxing)
 
-.debug_frame    0x00000000      0x124
+.debug_frame    0x00000000      0x1e4
  .debug_frame   0x00000000       0x60 build/gpio.o
- .debug_frame   0x00000060       0x58 build/main.o
+ .debug_frame   0x00000060       0x50 build/main.o
- .debug_frame   0x000000b8       0x6c build/startup.o
+ .debug_frame   0x000000b0       0x6c build/startup.o
+ .debug_frame   0x0000011c       0x50 build/timer.o
+ .debug_frame   0x0000016c       0x78 build/usart.o

build/gpio.S

@@ -182,16 +182,16 @@ gpio_write:
 	.file 4 "src/gpio.h"
 	.section	.debug_info,"",%progbits
 .Ldebug_info0:
-	.4byte	0x216
+	.4byte	0x201
 	.2byte	0x5
 	.byte	0x1
 	.byte	0x4
 	.4byte	.Ldebug_abbrev0
-	.uleb128 0x9
+	.uleb128 0x8
-	.4byte	.LASF894
+	.4byte	.LASF908
 	.byte	0x1d
-	.4byte	.LASF895
+	.4byte	.LASF909
-	.4byte	.LASF896
+	.4byte	.LASF910
 	.4byte	.LLRL0
 	.4byte	0
 	.4byte	.Ldebug_line0
@@ -199,17 +199,17 @@ gpio_write:
 	.uleb128 0x1
 	.byte	0x1
 	.byte	0x6
-	.4byte	.LASF863
+	.4byte	.LASF877
 	.uleb128 0x1
 	.byte	0x1
 	.byte	0x8
-	.4byte	.LASF864
+	.4byte	.LASF878
 	.uleb128 0x1
 	.byte	0x2
 	.byte	0x5
-	.4byte	.LASF865
+	.4byte	.LASF879
 	.uleb128 0x3
-	.4byte	.LASF868
+	.4byte	.LASF882
 	.byte	0x2
 	.byte	0x39
 	.byte	0x1c
@@ -217,13 +217,13 @@ gpio_write:
 	.uleb128 0x1
 	.byte	0x2
 	.byte	0x7
-	.4byte	.LASF866
+	.4byte	.LASF880
 	.uleb128 0x1
 	.byte	0x4
 	.byte	0x5
-	.4byte	.LASF867
+	.4byte	.LASF881
 	.uleb128 0x3
-	.4byte	.LASF869
+	.4byte	.LASF883
 	.byte	0x2
 	.byte	0x4f
 	.byte	0x1b
@@ -231,21 +231,21 @@ gpio_write:
 	.uleb128 0x1
 	.byte	0x4
 	.byte	0x7
-	.4byte	.LASF870
+	.4byte	.LASF884
 	.uleb128 0x1
 	.byte	0x8
 	.byte	0x5
-	.4byte	.LASF871
+	.4byte	.LASF885
 	.uleb128 0x1
 	.byte	0x8
 	.byte	0x7
-	.4byte	.LASF872
+	.4byte	.LASF886
-	.uleb128 0xa
+	.uleb128 0x9
 	.byte	0x4
 	.byte	0x5
 	.ascii	"int\000"
 	.uleb128 0x3
-	.4byte	.LASF873
+	.4byte	.LASF887
 	.byte	0x2
 	.byte	0xe8
 	.byte	0x16
@@ -253,123 +253,114 @@ gpio_write:
 	.uleb128 0x1
 	.byte	0x4
 	.byte	0x7
-	.4byte	.LASF874
+	.4byte	.LASF888
 	.uleb128 0x3
-	.4byte	.LASF875
+	.4byte	.LASF889
 	.byte	0x3
 	.byte	0x24
 	.byte	0x14
 	.4byte	0x3f
 	.uleb128 0x3
-	.4byte	.LASF876
+	.4byte	.LASF890
 	.byte	0x3
 	.byte	0x30
 	.byte	0x14
 	.4byte	0x59
-	.uleb128 0x6
+	.uleb128 0xa
 	.4byte	0xa0
 	.uleb128 0x3
-	.4byte	.LASF877
+	.4byte	.LASF891
 	.byte	0x3
 	.byte	0x52
 	.byte	0x15
 	.4byte	0x81
 	.uleb128 0xb
-	.4byte	.LASF893
+	.4byte	.LASF907
-	.byte	0x30
+	.byte	0x28
 	.byte	0x4
 	.byte	0x7
 	.byte	0x8
 	.4byte	0x139
 	.uleb128 0x2
-	.4byte	.LASF878
+	.4byte	.LASF892
 	.byte	0x8
 	.4byte	0xac
 	.byte	0
 	.uleb128 0x2
-	.4byte	.LASF879
+	.4byte	.LASF893
 	.byte	0x9
 	.4byte	0xac
 	.byte	0x4
 	.uleb128 0x2
-	.4byte	.LASF880
+	.4byte	.LASF894
 	.byte	0xa
 	.4byte	0xac
 	.byte	0x8
 	.uleb128 0x2
-	.4byte	.LASF881
+	.4byte	.LASF895
 	.byte	0xb
 	.4byte	0xac
 	.byte	0xc
-	.uleb128 0x7
+	.uleb128 0x6
 	.ascii	"IDR\000"
 	.byte	0xc
 	.4byte	0xac
 	.byte	0x10
-	.uleb128 0x7
+	.uleb128 0x6
 	.ascii	"ODR\000"
 	.byte	0xd
 	.4byte	0xac
 	.byte	0x14
 	.uleb128 0x2
-	.4byte	.LASF882
+	.4byte	.LASF896
 	.byte	0xe
 	.4byte	0xac
 	.byte	0x18
 	.uleb128 0x2
-	.4byte	.LASF883
+	.4byte	.LASF897
 	.byte	0xf
 	.4byte	0xac
 	.byte	0x1c
 	.uleb128 0x2
-	.4byte	.LASF884
+	.4byte	.LASF898
 	.byte	0x10
-	.4byte	0x149
+	.4byte	0xac
 	.byte	0x20
 	.uleb128 0x2
-	.4byte	.LASF885
+	.4byte	.LASF899
 	.byte	0x11
-	.4byte	0x149
+	.4byte	0xac
-	.byte	0x28
+	.byte	0x24
 	.byte	0
 	.uleb128 0xc
-	.4byte	0xac
-	.4byte	0x149
-	.uleb128 0xd
-	.4byte	0x8d
-	.byte	0x1
-	.byte	0
-	.uleb128 0x6
-	.4byte	0x139
-	.uleb128 0xe
 	.byte	0x7
 	.byte	0x1
 	.4byte	0x31
 	.byte	0x4
-	.byte	0x20
+	.byte	0x3a
 	.byte	0xe
-	.4byte	0x175
+	.4byte	0x160
 	.uleb128 0x4
-	.4byte	.LASF886
+	.4byte	.LASF900
 	.byte	0
 	.uleb128 0x4
-	.4byte	.LASF887
+	.4byte	.LASF901
 	.byte	0x1
 	.uleb128 0x4
-	.4byte	.LASF888
+	.4byte	.LASF902
 	.byte	0x2
 	.uleb128 0x4
-	.4byte	.LASF889
+	.4byte	.LASF903
 	.byte	0x3
 	.byte	0
 	.uleb128 0x3
-	.4byte	.LASF890
+	.4byte	.LASF904
 	.byte	0x4
-	.byte	0x25
+	.byte	0x3f
 	.byte	0x3
-	.4byte	0x14e
+	.4byte	0x139
-	.uleb128 0xf
+	.uleb128 0xd
-	.4byte	.LASF897
+	.4byte	.LASF911
 	.byte	0x1
 	.byte	0xd
 	.byte	0x6
@@ -377,7 +368,7 @@ gpio_write:
 	.4byte	.LFE1-.LFB1
 	.uleb128 0x1
 	.byte	0x9c
-	.4byte	0x1c1
+	.4byte	0x1ac
 	.uleb128 0x5
 	.ascii	"pin\000"
 	.byte	0xd
@@ -390,14 +381,14 @@ gpio_write:
 	.ascii	"val\000"
 	.byte	0xd
 	.byte	0x23
-	.4byte	0x1c1
+	.4byte	0x1ac
 	.uleb128 0x2
 	.byte	0x91
 	.sleb128 -19
-	.uleb128 0x8
+	.uleb128 0x7
-	.4byte	.LASF893
+	.4byte	.LASF907
 	.byte	0xe
-	.4byte	0x1c8
+	.4byte	0x1b3
 	.uleb128 0x2
 	.byte	0x91
 	.sleb128 -12
@@ -405,12 +396,12 @@ gpio_write:
 	.uleb128 0x1
 	.byte	0x1
 	.byte	0x2
-	.4byte	.LASF891
+	.4byte	.LASF905
-	.uleb128 0x10
+	.uleb128 0xe
 	.byte	0x4
 	.4byte	0xbd
-	.uleb128 0x11
+	.uleb128 0xf
-	.4byte	.LASF898
+	.4byte	.LASF912
 	.byte	0x1
 	.byte	0x6
 	.byte	0x6
@@ -426,23 +417,23 @@ gpio_write:
 	.uleb128 0x2
 	.byte	0x91
 	.sleb128 -18
-	.uleb128 0x12
+	.uleb128 0x10
-	.4byte	.LASF892
+	.4byte	.LASF906
 	.byte	0x1
 	.byte	0x6
 	.byte	0x2c
-	.4byte	0x175
+	.4byte	0x160
 	.uleb128 0x2
 	.byte	0x91
 	.sleb128 -19
-	.uleb128 0x8
+	.uleb128 0x7
-	.4byte	.LASF893
+	.4byte	.LASF907
 	.byte	0x7
-	.4byte	0x1c8
+	.4byte	0x1b3
 	.uleb128 0x2
 	.byte	0x91
 	.sleb128 -12
-	.uleb128 0x13
+	.uleb128 0x11
 	.ascii	"pn\000"
 	.byte	0x1
 	.byte	0x8
@@ -528,13 +519,6 @@ gpio_write:
 	.byte	0
 	.byte	0
 	.uleb128 0x6
-	.uleb128 0x35
-	.byte	0
-	.uleb128 0x49
-	.uleb128 0x13
-	.byte	0
-	.byte	0
-	.uleb128 0x7
 	.uleb128 0xd
 	.byte	0
 	.uleb128 0x3
@@ -553,7 +537,7 @@ gpio_write:
 	.uleb128 0xb
 	.byte	0
 	.byte	0
-	.uleb128 0x8
+	.uleb128 0x7
 	.uleb128 0x34
 	.byte	0
 	.uleb128 0x3
@@ -572,7 +556,7 @@ gpio_write:
 	.uleb128 0x18
 	.byte	0
 	.byte	0
-	.uleb128 0x9
+	.uleb128 0x8
 	.uleb128 0x11
 	.byte	0x1
 	.uleb128 0x25
@@ -593,7 +577,7 @@ gpio_write:
 	.uleb128 0x17
 	.byte	0
 	.byte	0
-	.uleb128 0xa
+	.uleb128 0x9
 	.uleb128 0x24
 	.byte	0
 	.uleb128 0xb
@@ -604,6 +588,13 @@ gpio_write:
 	.uleb128 0x8
 	.byte	0
 	.byte	0
+	.uleb128 0xa
+	.uleb128 0x35
+	.byte	0
+	.uleb128 0x49
+	.uleb128 0x13
+	.byte	0
+	.byte	0
 	.uleb128 0xb
 	.uleb128 0x13
 	.byte	0x1
@@ -622,24 +613,6 @@ gpio_write:
 	.byte	0
 	.byte	0
 	.uleb128 0xc
-	.uleb128 0x1
-	.byte	0x1
-	.uleb128 0x49
-	.uleb128 0x13
-	.uleb128 0x1
-	.uleb128 0x13
-	.byte	0
-	.byte	0
-	.uleb128 0xd
-	.uleb128 0x21
-	.byte	0
-	.uleb128 0x49
-	.uleb128 0x13
-	.uleb128 0x2f
-	.uleb128 0xb
-	.byte	0
-	.byte	0
-	.uleb128 0xe
 	.uleb128 0x4
 	.byte	0x1
 	.uleb128 0x3e
@@ -658,7 +631,7 @@ gpio_write:
 	.uleb128 0x13
 	.byte	0
 	.byte	0
-	.uleb128 0xf
+	.uleb128 0xd
 	.uleb128 0x2e
 	.byte	0x1
 	.uleb128 0x3f
@@ -685,7 +658,7 @@ gpio_write:
 	.uleb128 0x13
 	.byte	0
 	.byte	0
-	.uleb128 0x10
+	.uleb128 0xe
 	.uleb128 0xf
 	.byte	0
 	.uleb128 0xb
@@ -694,7 +667,7 @@ gpio_write:
 	.uleb128 0x13
 	.byte	0
 	.byte	0
-	.uleb128 0x11
+	.uleb128 0xf
 	.uleb128 0x2e
 	.byte	0x1
 	.uleb128 0x3f
@@ -719,7 +692,7 @@ gpio_write:
 	.uleb128 0x19
 	.byte	0
 	.byte	0
-	.uleb128 0x12
+	.uleb128 0x10
 	.uleb128 0x5
 	.byte	0
 	.uleb128 0x3
@@ -736,7 +709,7 @@ gpio_write:
 	.uleb128 0x18
 	.byte	0
 	.byte	0
-	.uleb128 0x13
+	.uleb128 0x11
 	.uleb128 0x34
 	.byte	0
 	.uleb128 0x3
@@ -3552,7 +3525,7 @@ gpio_write:
 	.uleb128 0x32
 	.4byte	.LASF854
 	.byte	0
-	.section	.debug_macro,"G",%progbits,wm4.gpio.h.2.d78c96d470f4347bf35ed0e3d72ef81e,comdat
+	.section	.debug_macro,"G",%progbits,wm4.gpio.h.2.618f9f202e3921ef232a09b28d15fb8b,comdat
 .Ldebug_macro15:
 	.2byte	0x5
 	.byte	0
@@ -3566,10 +3539,10 @@ gpio_write:
 	.uleb128 0x15
 	.4byte	.LASF857
 	.byte	0x5
-	.uleb128 0x16
+	.uleb128 0x18
 	.4byte	.LASF858
 	.byte	0x5
-	.uleb128 0x18
+	.uleb128 0x19
 	.4byte	.LASF859
 	.byte	0x5
 	.uleb128 0x1a
@@ -3578,8 +3551,50 @@ gpio_write:
 	.uleb128 0x1c
 	.4byte	.LASF861
 	.byte	0x5
-	.uleb128 0x1e
+	.uleb128 0x1d
 	.4byte	.LASF862
+	.byte	0x5
+	.uleb128 0x1e
+	.4byte	.LASF863
+	.byte	0x5
+	.uleb128 0x21
+	.4byte	.LASF864
+	.byte	0x5
+	.uleb128 0x22
+	.4byte	.LASF865
+	.byte	0x5
+	.uleb128 0x23
+	.4byte	.LASF866
+	.byte	0x5
+	.uleb128 0x25
+	.4byte	.LASF867
+	.byte	0x5
+	.uleb128 0x26
+	.4byte	.LASF868
+	.byte	0x5
+	.uleb128 0x27
+	.4byte	.LASF869
+	.byte	0x5
+	.uleb128 0x2e
+	.4byte	.LASF870
+	.byte	0x5
+	.uleb128 0x2f
+	.4byte	.LASF871
+	.byte	0x5
+	.uleb128 0x30
+	.4byte	.LASF872
+	.byte	0x5
+	.uleb128 0x32
+	.4byte	.LASF873
+	.byte	0x5
+	.uleb128 0x34
+	.4byte	.LASF874
+	.byte	0x5
+	.uleb128 0x36
+	.4byte	.LASF875
+	.byte	0x5
+	.uleb128 0x38
+	.4byte	.LASF876
 	.byte	0
 	.section	.debug_line,"",%progbits
 .Ldebug_line0:
@@ -3624,7 +3639,7 @@ gpio_write:
 	.ascii	"__PTRDIFF_MAX__ 0x7fffffff\000"
 .LASF541:
 	.ascii	"_LONG_DOUBLE long double\000"
-.LASF893:
+.LASF907:
 	.ascii	"gpio\000"
 .LASF591:
 	.ascii	"INT_LEAST8_MIN (-__INT_LEAST8_MAX__ - 1)\000"
@@ -3632,7 +3647,7 @@ gpio_write:
 	.ascii	"_UINT32_T_DECLARED \000"
 .LASF90:
 	.ascii	"__INTMAX_MAX__ 0x7fffffffffffffffLL\000"
-.LASF888:
+.LASF902:
 	.ascii	"GPIO_MODE_AF\000"
 .LASF335:
 	.ascii	"__TQ_IBIT__ 0\000"
@@ -3696,6 +3711,8 @@ gpio_write:
 	.ascii	"PRIXFAST32 __PRI32FAST(X)\000"
 .LASF525:
 	.ascii	"__INT8 \"hh\"\000"
+.LASF860:
+	.ascii	"GPIO_MODER_MODER3_AF (0b10)\000"
 .LASF47:
 	.ascii	"__UINT8_TYPE__ unsigned char\000"
 .LASF368:
@@ -3704,6 +3721,8 @@ gpio_write:
 	.ascii	"INT_LEAST16_MAX (__INT_LEAST16_MAX__)\000"
 .LASF703:
 	.ascii	"SCNiFAST8 __SCN8FAST(i)\000"
+.LASF856:
+	.ascii	"GPIOA_BASE_ADDR (0x40020000U)\000"
 .LASF120:
 	.ascii	"__UINT_LEAST16_MAX__ 0xffff\000"
 .LASF616:
@@ -3746,11 +3765,13 @@ gpio_write:
 	.ascii	"__need_wchar_t\000"
 .LASF199:
 	.ascii	"__FLT32_MIN_EXP__ (-125)\000"
-.LASF894:
+.LASF908:
 	.ascii	"GNU C2X 12.3.1 20230626 -mcpu=cortex-m4 -mthumb -mf"
 	.ascii	"loat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp "
 	.ascii	"-g3 -ggdb -O0 -std=c2x -ffunction-sections -fdata-s"
 	.ascii	"ections -fno-builtin -fno-common\000"
+.LASF864:
+	.ascii	"GPIO_AFRL_AFRL3_BIT 12\000"
 .LASF595:
 	.ascii	"INT16_MAX (__INT16_MAX__)\000"
 .LASF502:
@@ -3831,7 +3852,7 @@ gpio_write:
 	.ascii	"__INT64 \"ll\"\000"
 .LASF138:
 	.ascii	"__INTPTR_MAX__ 0x7fffffff\000"
-.LASF858:
+.LASF872:
 	.ascii	"GPIO(port) ((struct gpio*)(uintptr_t)(GPIO_BASE_ADD"
 	.ascii	"R + (GPIO_PORT_OFFSET * port)))\000"
 .LASF499:
@@ -3867,7 +3888,7 @@ gpio_write:
 	.ascii	"PRId64 __PRI64(d)\000"
 .LASF302:
 	.ascii	"__UACCUM_IBIT__ 16\000"
-.LASF867:
+.LASF881:
 	.ascii	"long int\000"
 .LASF818:
 	.ascii	"PRIXFAST64 __PRI64FAST(X)\000"
@@ -3903,6 +3924,8 @@ gpio_write:
 	.ascii	"__GCC_ATOMIC_BOOL_LOCK_FREE 2\000"
 .LASF554:
 	.ascii	"___int64_t_defined 1\000"
+.LASF863:
+	.ascii	"GPIO_MODER_MODER2_AF (0b10)\000"
 .LASF432:
 	.ascii	"__ARM_NEON__\000"
 .LASF587:
@@ -3963,7 +3986,7 @@ gpio_write:
 	.ascii	"PRIoLEAST16 __PRI16LEAST(o)\000"
 .LASF458:
 	.ascii	"__NEWLIB__ 4\000"
-.LASF886:
+.LASF900:
 	.ascii	"GPIO_MODE_INPUT\000"
 .LASF720:
 	.ascii	"SCNi16 __SCN16(i)\000"
@@ -3973,7 +3996,7 @@ gpio_write:
 	.ascii	"__FLT_DECIMAL_DIG__ 9\000"
 .LASF562:
 	.ascii	"_UINT8_T_DECLARED \000"
-.LASF863:
+.LASF877:
 	.ascii	"signed char\000"
 .LASF805:
 	.ascii	"PRIuLEAST64 __PRI64LEAST(u)\000"
@@ -3985,7 +4008,7 @@ gpio_write:
 	.ascii	"__ARM_FEATURE_FMA 1\000"
 .LASF364:
 	.ascii	"__GNUC_STDC_INLINE__ 1\000"
-.LASF890:
+.LASF904:
 	.ascii	"GPIO_MODE\000"
 .LASF256:
 	.ascii	"__FRACT_FBIT__ 15\000"
@@ -4007,9 +4030,11 @@ gpio_write:
 	.ascii	"__SACCUM_MAX__ 0X7FFFP-7HK\000"
 .LASF219:
 	.ascii	"__FLT64_MAX_10_EXP__ 308\000"
+.LASF868:
+	.ascii	"GPIO_AFRL_AFRL2_MASK (0b1111)\000"
 .LASF65:
 	.ascii	"__UINT_FAST32_TYPE__ unsigned int\000"
-.LASF864:
+.LASF878:
 	.ascii	"unsigned char\000"
 .LASF3:
 	.ascii	"__STDC_UTF_32__ 1\000"
@@ -4057,13 +4082,13 @@ gpio_write:
 	.ascii	"__int_fast64_t_defined 1\000"
 .LASF837:
 	.ascii	"__PRIPTR(x) __STRINGIFY(x)\000"
-.LASF875:
+.LASF889:
 	.ascii	"uint16_t\000"
 .LASF417:
 	.ascii	"__thumb2__ 1\000"
 .LASF321:
 	.ascii	"__ULLACCUM_FBIT__ 32\000"
-.LASF891:
+.LASF905:
 	.ascii	"_Bool\000"
 .LASF366:
 	.ascii	"__STRICT_ANSI__ 1\000"
@@ -4081,7 +4106,7 @@ gpio_write:
 	.ascii	"__PRAGMA_REDEFINE_EXTNAME 1\000"
 .LASF36:
 	.ascii	"__WCHAR_TYPE__ unsigned int\000"
-.LASF887:
+.LASF901:
 	.ascii	"GPIO_MODE_OUTPUT\000"
 .LASF357:
 	.ascii	"__USA_IBIT__ 16\000"
@@ -4119,7 +4144,7 @@ gpio_write:
 	.ascii	"__SCN64(x) __INT64 __STRINGIFY(x)\000"
 .LASF646:
 	.ascii	"_GCC_WRAP_STDINT_H \000"
-.LASF868:
+.LASF882:
 	.ascii	"__uint16_t\000"
 .LASF224:
 	.ascii	"__FLT64_EPSILON__ 2.2204460492503131e-16F64\000"
@@ -4147,7 +4172,7 @@ gpio_write:
 	.ascii	"INTMAX_MAX (__INTMAX_MAX__)\000"
 .LASF601:
 	.ascii	"INT32_MAX (__INT32_MAX__)\000"
-.LASF859:
+.LASF873:
 	.ascii	"BIT(x) (1 << x)\000"
 .LASF469:
 	.ascii	"_MB_LEN_MAX 8\000"
@@ -4165,6 +4190,8 @@ gpio_write:
 	.ascii	"_END_STD_C \000"
 .LASF852:
 	.ascii	"true ((_Bool)+1u)\000"
+.LASF865:
+	.ascii	"GPIO_AFRL_AFRL3_MASK (0b1111)\000"
 .LASF599:
 	.ascii	"UINT_LEAST16_MAX (__UINT_LEAST16_MAX__)\000"
 .LASF123:
@@ -4177,7 +4204,7 @@ gpio_write:
 	.ascii	"__FLT_EPSILON__ 1.1920928955078125e-7F\000"
 .LASF376:
 	.ascii	"__GCC_ATOMIC_SHORT_LOCK_FREE 2\000"
-.LASF860:
+.LASF874:
 	.ascii	"PIN(port,num) ((((port) - 'A') << 8) | num)\000"
 .LASF806:
 	.ascii	"PRIxLEAST64 __PRI64LEAST(x)\000"
@@ -4243,6 +4270,8 @@ gpio_write:
 	.ascii	"__FP_FAST_FMAF 1\000"
 .LASF628:
 	.ascii	"SIG_ATOMIC_MIN (-__STDINT_EXP(INT_MAX) - 1)\000"
+.LASF869:
+	.ascii	"GPIO_AFRL_AFRL2_USART2_TX (0b0111)\000"
 .LASF564:
 	.ascii	"_INT16_T_DECLARED \000"
 .LASF245:
@@ -4285,6 +4314,8 @@ gpio_write:
 	.ascii	"INT64_C(x) __INT64_C(x)\000"
 .LASF615:
 	.ascii	"INT_FAST16_MIN (-__INT_FAST16_MAX__ - 1)\000"
+.LASF862:
+	.ascii	"GPIO_MODER_MODER2_MASK (0b11)\000"
 .LASF106:
 	.ascii	"__INT_LEAST8_MAX__ 0x7f\000"
 .LASF383:
@@ -4333,7 +4364,7 @@ gpio_write:
 	.ascii	"___int8_t_defined 1\000"
 .LASF248:
 	.ascii	"__SFRACT_MIN__ (-0.5HR-0.5HR)\000"
-.LASF870:
+.LASF884:
 	.ascii	"long unsigned int\000"
 .LASF349:
 	.ascii	"__SA_IBIT__ 16\000"
@@ -4349,7 +4380,7 @@ gpio_write:
 	.ascii	"__ARM_FP16_FORMAT_IEEE\000"
 .LASF48:
 	.ascii	"__UINT16_TYPE__ short unsigned int\000"
-.LASF897:
+.LASF911:
 	.ascii	"gpio_write\000"
 .LASF569:
 	.ascii	"__int32_t_defined 1\000"
@@ -4361,7 +4392,7 @@ gpio_write:
 	.ascii	"__FLT_EVAL_METHOD_TS_18661_3__ 0\000"
 .LASF521:
 	.ascii	"int +2\000"
-.LASF896:
+.LASF910:
 	.ascii	"/home/alex/code/own/c-compile-experiments\000"
 .LASF636:
 	.ascii	"INT8_C(x) __INT8_C(x)\000"
@@ -4395,7 +4426,7 @@ gpio_write:
 	.ascii	"SCNx8 __SCN8(x)\000"
 .LASF208:
 	.ascii	"__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32\000"
-.LASF898:
+.LASF912:
 	.ascii	"gpio_set_mode\000"
 .LASF125:
 	.ascii	"__UINT64_C(c) c ## ULL\000"
@@ -4407,6 +4438,8 @@ gpio_write:
 	.ascii	"__USFRACT_FBIT__ 8\000"
 .LASF191:
 	.ascii	"__LDBL_EPSILON__ 2.2204460492503131e-16L\000"
+.LASF857:
+	.ascii	"GPIOA ((struct gpio *) GPIOA_BASE_ADDR)\000"
 .LASF729:
 	.ascii	"PRIXLEAST16 __PRI16LEAST(X)\000"
 .LASF622:
@@ -4415,7 +4448,7 @@ gpio_write:
 	.ascii	"__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2\000"
 .LASF789:
 	.ascii	"__PRI64FAST(x) __FAST64 __STRINGIFY(x)\000"
-.LASF877:
+.LASF891:
 	.ascii	"uintptr_t\000"
 .LASF168:
 	.ascii	"__DBL_MAX_EXP__ 1024\000"
@@ -4463,7 +4496,7 @@ gpio_write:
 	.ascii	"PRIX32 __PRI32(X)\000"
 .LASF773:
 	.ascii	"SCNxLEAST32 __SCN32LEAST(x)\000"
-.LASF880:
+.LASF894:
 	.ascii	"OSPEEDR\000"
 .LASF711:
 	.ascii	"__SCN16LEAST(x) __LEAST16 __STRINGIFY(x)\000"
@@ -4493,7 +4526,7 @@ gpio_write:
 	.ascii	"__ULACCUM_MIN__ 0.0ULK\000"
 .LASF461:
 	.ascii	"_ATEXIT_DYNAMIC_ALLOC 1\000"
-.LASF869:
+.LASF883:
 	.ascii	"__uint32_t\000"
 .LASF188:
 	.ascii	"__LDBL_MAX__ 1.7976931348623157e+308L\000"
@@ -4503,7 +4536,7 @@ gpio_write:
 	.ascii	"__FLT_RADIX__ 2\000"
 .LASF454:
 	.ascii	"_INTTYPES_H \000"
-.LASF871:
+.LASF885:
 	.ascii	"long long int\000"
 .LASF401:
 	.ascii	"__ARM_FEATURE_CMSE\000"
@@ -4539,6 +4572,8 @@ gpio_write:
 	.ascii	"__WCHAR_T \000"
 .LASF223:
 	.ascii	"__FLT64_MIN__ 2.2250738585072014e-308F64\000"
+.LASF866:
+	.ascii	"GPIO_AFRL_AFRL3_USART2_RX (0b0111)\000"
 .LASF553:
 	.ascii	"___int32_t_defined 1\000"
 .LASF83:
@@ -4608,7 +4643,7 @@ gpio_write:
 	.ascii	"\000"
 .LASF582:
 	.ascii	"__int_fast16_t_defined 1\000"
-.LASF878:
+.LASF892:
 	.ascii	"MODER\000"
 .LASF482:
 	.ascii	"__FLOAT_TYPE float\000"
@@ -4619,9 +4654,9 @@ gpio_write:
 	.ascii	"L)\000"
 .LASF607:
 	.ascii	"INT64_MAX (__INT64_MAX__)\000"
-.LASF874:
+.LASF888:
 	.ascii	"unsigned int\000"
-.LASF873:
+.LASF887:
 	.ascii	"__uintptr_t\000"
 .LASF459:
 	.ascii	"__NEWLIB_MINOR__ 3\000"
@@ -4653,7 +4688,7 @@ gpio_write:
 	.ascii	"__CHAR_BIT__ 8\000"
 .LASF143:
 	.ascii	"__FLT_EVAL_METHOD__ 0\000"
-.LASF865:
+.LASF879:
 	.ascii	"short int\000"
 .LASF685:
 	.ascii	"PRIdLEAST8 __PRI8LEAST(d)\000"
@@ -4779,6 +4814,8 @@ gpio_write:
 	.ascii	"__UFRACT_IBIT__ 0\000"
 .LASF399:
 	.ascii	"__ARM_32BIT_STATE 1\000"
+.LASF861:
+	.ascii	"GPIO_MODER_MODER2_BIT 4\000"
 .LASF107:
 	.ascii	"__INT8_C(c) c\000"
 .LASF267:
@@ -4791,12 +4828,14 @@ gpio_write:
 	.ascii	"SCNuFAST16 __SCN16FAST(u)\000"
 .LASF801:
 	.ascii	"SCNx64 __SCN64(x)\000"
-.LASF862:
+.LASF876:
 	.ascii	"PINPORT(pin) (pin >> 8)\000"
 .LASF198:
 	.ascii	"__FLT32_DIG__ 6\000"
 .LASF645:
 	.ascii	"UINTMAX_C(x) __UINTMAX_C(x)\000"
+.LASF859:
+	.ascii	"GPIO_MODER_MODER3_MASK (0b11)\000"
 .LASF623:
 	.ascii	"UINT_FAST64_MAX (__UINT_FAST64_MAX__)\000"
 .LASF515:
@@ -4839,7 +4878,7 @@ gpio_write:
 	.ascii	"__ORDER_LITTLE_ENDIAN__ 1234\000"
 .LASF155:
 	.ascii	"__FLT_NORM_MAX__ 3.4028234663852886e+38F\000"
-.LASF872:
+.LASF886:
 	.ascii	"long long unsigned int\000"
 .LASF611:
 	.ascii	"UINT_LEAST64_MAX (__UINT_LEAST64_MAX__)\000"
@@ -4869,6 +4908,8 @@ gpio_write:
 	.ascii	"SCNdFAST32 __SCN32FAST(d)\000"
 .LASF339:
 	.ascii	"__UHQ_IBIT__ 0\000"
+.LASF858:
+	.ascii	"GPIO_MODER_MODER3_BIT 7\000"
 .LASF60:
 	.ascii	"__INT_FAST16_TYPE__ int\000"
 .LASF631:
@@ -4917,11 +4958,11 @@ gpio_write:
 	.ascii	"SCNdFAST8 __SCN8FAST(d)\000"
 .LASF576:
 	.ascii	"_UINTPTR_T_DECLARED \000"
-.LASF885:
+.LASF899:
 	.ascii	"AFRH\000"
 .LASF314:
 	.ascii	"__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULK\000"
-.LASF884:
+.LASF898:
 	.ascii	"AFRL\000"
 .LASF273:
 	.ascii	"__ULFRACT_MIN__ 0.0ULR\000"
@@ -4935,7 +4976,7 @@ gpio_write:
 	.ascii	"__INT32_TYPE__ long int\000"
 .LASF118:
 	.ascii	"__UINT_LEAST8_MAX__ 0xff\000"
-.LASF883:
+.LASF897:
 	.ascii	"LCKR\000"
 .LASF520:
 	.ascii	"__int20__ +2\000"
@@ -4981,7 +5022,7 @@ gpio_write:
 	.ascii	"__QQ_IBIT__ 0\000"
 .LASF763:
 	.ascii	"PRIdLEAST32 __PRI32LEAST(d)\000"
-.LASF879:
+.LASF893:
 	.ascii	"OTYPER\000"
 .LASF811:
 	.ascii	"SCNuLEAST64 __SCN64LEAST(u)\000"
@@ -5001,11 +5042,11 @@ gpio_write:
 	.ascii	"__GNUC_MINOR__ 3\000"
 .LASF57:
 	.ascii	"__UINT_LEAST32_TYPE__ long unsigned int\000"
-.LASF895:
+.LASF909:
 	.ascii	"src/gpio.c\000"
 .LASF405:
 	.ascii	"__ARM_FEATURE_NUMERIC_MAXMIN\000"
-.LASF856:
+.LASF870:
 	.ascii	"GPIO_BASE_ADDR (0x40020000U)\000"
 .LASF38:
 	.ascii	"__INTMAX_TYPE__ long long int\000"
@@ -5057,7 +5098,7 @@ gpio_write:
 	.ascii	"__SCN8(x) __INT8 __STRINGIFY(x)\000"
 .LASF23:
 	.ascii	"__SIZEOF_SIZE_T__ 4\000"
-.LASF857:
+.LASF871:
 	.ascii	"GPIO_PORT_OFFSET (0x400U)\000"
 .LASF50:
 	.ascii	"__UINT64_TYPE__ long long unsigned int\000"
@@ -5067,6 +5108,8 @@ gpio_write:
 	.ascii	"__INT64_C(c) c ## LL\000"
 .LASF699:
 	.ascii	"PRIuFAST8 __PRI8FAST(u)\000"
+.LASF867:
+	.ascii	"GPIO_AFRL_AFRL2_BIT 8\000"
 .LASF190:
 	.ascii	"__LDBL_MIN__ 2.2250738585072014e-308L\000"
 .LASF445:
@@ -5075,7 +5118,7 @@ gpio_write:
 	.ascii	"__ACCUM_IBIT__ 16\000"
 .LASF509:
 	.ascii	"unsigned\000"
-.LASF881:
+.LASF895:
 	.ascii	"PUPDR\000"
 .LASF835:
 	.ascii	"SCNuMAX __SCNMAX(u)\000"
@@ -5085,7 +5128,7 @@ gpio_write:
 	.ascii	"_ATTRIBUTE(attrs) __attribute__ (attrs)\000"
 .LASF359:
 	.ascii	"__UDA_IBIT__ 32\000"
-.LASF892:
+.LASF906:
 	.ascii	"mode\000"
 .LASF586:
 	.ascii	"INTPTR_MAX (__INTPTR_MAX__)\000"
@@ -5099,7 +5142,7 @@ gpio_write:
 	.ascii	"__UHQ_FBIT__ 16\000"
 .LASF443:
 	.ascii	"__ARM_FEATURE_COPROC\000"
-.LASF889:
+.LASF903:
 	.ascii	"GPIO_MODE_ANALOG\000"
 .LASF177:
 	.ascii	"__DBL_HAS_INFINITY__ 1\000"
@@ -5137,7 +5180,7 @@ gpio_write:
 	.ascii	"__FAST8 \000"
 .LASF496:
 	.ascii	"__XSI_VISIBLE 0\000"
-.LASF882:
+.LASF896:
 	.ascii	"BSRR\000"
 .LASF794:
 	.ascii	"PRIu64 __PRI64(u)\000"
@@ -5225,7 +5268,7 @@ gpio_write:
 	.ascii	"PRIx32 __PRI32(x)\000"
 .LASF278:
 	.ascii	"__LLFRACT_MIN__ (-0.5LLR-0.5LLR)\000"
-.LASF876:
+.LASF890:
 	.ascii	"uint32_t\000"
 .LASF689:
 	.ascii	"PRIxLEAST8 __PRI8LEAST(x)\000"
@@ -5273,13 +5316,13 @@ gpio_write:
 	.ascii	"__INT_LEAST16_TYPE__ short int\000"
 .LASF326:
 	.ascii	"__QQ_FBIT__ 7\000"
-.LASF861:
+.LASF875:
 	.ascii	"PINNUM(pin) (pin & 0b1111)\000"
 .LASF768:
 	.ascii	"PRIXLEAST32 __PRI32LEAST(X)\000"
 .LASF171:
 	.ascii	"__DBL_MAX__ ((double)1.7976931348623157e+308L)\000"
-.LASF866:
+.LASF880:
 	.ascii	"short unsigned int\000"
 .LASF276:
 	.ascii	"__LLFRACT_FBIT__ 63\000"

build/gpio.i

@@ -1995,10 +1995,36 @@ struct gpio {
   volatile uint32_t ODR;
   volatile uint32_t BSRR;
   volatile uint32_t LCKR;
-  volatile uint32_t AFRL[2];
+  volatile uint32_t AFRL;
-  volatile uint32_t AFRH[2];
+  volatile uint32_t AFRH;
 };
 
+#define GPIOA_BASE_ADDR (0x40020000U)
+#define GPIOA ((struct gpio *) GPIOA_BASE_ADDR)
+
+
+#define GPIO_MODER_MODER3_BIT 7
+#define GPIO_MODER_MODER3_MASK (0b11)
+#define GPIO_MODER_MODER3_AF (0b10)
+
+#define GPIO_MODER_MODER2_BIT 4
+#define GPIO_MODER_MODER2_MASK (0b11)
+#define GPIO_MODER_MODER2_AF (0b10)
+
+
+#define GPIO_AFRL_AFRL3_BIT 12
+#define GPIO_AFRL_AFRL3_MASK (0b1111)
+#define GPIO_AFRL_AFRL3_USART2_RX (0b0111)
+
+#define GPIO_AFRL_AFRL2_BIT 8
+#define GPIO_AFRL_AFRL2_MASK (0b1111)
+#define GPIO_AFRL_AFRL2_USART2_TX (0b0111)
+
+
+
+
+
+
 #define GPIO_BASE_ADDR (0x40020000U)
 #define GPIO_PORT_OFFSET (0x400U)
 #define GPIO(port) ((struct gpio*)(uintptr_t)(GPIO_BASE_ADDR + (GPIO_PORT_OFFSET * port)))
@@ -2020,9 +2046,9 @@ typedef enum {
 
 void gpio_set_mode(uint16_t pin, GPIO_MODE mode);
 void gpio_write(uint16_t pin, 
-# 40 "src/gpio.h" 3 4
+# 66 "src/gpio.h" 3 4
                              _Bool 
-# 40 "src/gpio.h"
+# 66 "src/gpio.h"
                                   val);
 # 5 "src/gpio.c" 2
 

build/main.i

@@ -1963,6 +1963,20 @@ extern intmax_t _wcstoimax_r(struct _reent *, const wchar_t *__restrict, wchar_t
 extern uintmax_t wcstoumax(const wchar_t *__restrict, wchar_t **__restrict, int);
 extern uintmax_t _wcstoumax_r(struct _reent *, const wchar_t *__restrict, wchar_t **__restrict, int);
 # 2 "src/main.c" 2
+# 1 "/nix/store/yr89i11mszv2az19r26l372zgaiivj1c-gcc-arm-embedded-12.3.rel1/lib/gcc/arm-none-eabi/12.3.1/include/stdbool.h" 1 3 4
+# 29 "/nix/store/yr89i11mszv2az19r26l372zgaiivj1c-gcc-arm-embedded-12.3.rel1/lib/gcc/arm-none-eabi/12.3.1/include/stdbool.h" 3 4
+#define _STDBOOL_H 
+
+
+
+#define bool _Bool
+
+#define true ((_Bool)+1u)
+#define false ((_Bool)+0u)
+# 50 "/nix/store/yr89i11mszv2az19r26l372zgaiivj1c-gcc-arm-embedded-12.3.rel1/lib/gcc/arm-none-eabi/12.3.1/include/stdbool.h" 3 4
+#define __bool_true_false_are_defined 1
+# 3 "src/main.c" 2
+
 # 1 "src/rcc.h" 1
 
 #define RCC_H_ 
@@ -2004,26 +2018,106 @@ struct rcc {
 
 #define RCC_BASE_ADDR (0x40023800U)
 #define RCC ((struct rcc *) RCC_BASE_ADDR)
-# 3 "src/main.c" 2
+
+
+
+#define RCC_CR_PLLRDY_BIT 25
+#define RCC_CR_PLLRDY_LOCKED (1 << RCC_CR_PLLRDY_BIT)
+
+
+#define RCC_CR_PLLON_BIT 24
+#define RCC_CR_PLLON_ON (1 << RCC_CR_PLLON_BIT)
+
+
+#define RCC_CR_HSERDY_BIT 17
+#define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT)
+
+
+#define RCC_CR_HSEON_BIT 16
+#define RCC_CR_HSEON_ON (1 << RCC_CR_HSEON_BIT)
+
+
+#define RCC_CR_HSIRDY_BIT 1
+#define RCC_CR_HSIRDY_READY (1 << RCC_CR_HSIRDY_BIT)
+
+
+#define RCC_CR_HSION_BIT 0
+#define RCC_CR_HSION_ON (1 << RCC_CR_HSION_BIT)
+
+
+#define RCC_PLLCFGR_PLLQ_BIT 24
+#define RCC_PLLCFGR_PLLQ_MASK (0b1111)
+#define RCC_PLLCFGR_PLLQ(q) ((q & RCC_PLLCFGR_PLLQ_MASK) << RCC_PLLCFGR_PLLQ_BIT)
+
+#define RCC_PLLCFGR_PLLSRC_BIT 22
+#define RCC_PLLCFGR_PLLSRC_HSE (1 << RCC_PLLCFGR_PLLSRC_BIT)
+
+#define RCC_PLLCFGR_PLLP_BIT 16
+#define RCC_PLLCFGR_PLLP_MASK (0b11)
+#define RCC_PLLCFGR_PLLP(p) ((p & RCC_PLLCFGR_PLLP_MASK) << RCC_PLLCFGR_PLLP_BIT)
+
+#define RCC_PLLCFGR_PLLN_BIT 6
+#define RCC_PLLCFGR_PLLN_MASK (0b111111111)
+#define RCC_PLLCFGR_PLLN(n) ((n & RCC_PLLCFGR_PLLN_MASK) << RCC_PLLCFGR_PLLN_BIT)
+
+#define RCC_PLLCFGR_PLLM_BIT 0
+#define RCC_PLLCFGR_PLLM_MASK (0b111111)
+#define RCC_PLLCFGR_PLLM(m) ((m & RCC_PLLCFGR_PLLM_MASK) << RCC_PLLCFGR_PLLM_BIT)
+
+
+
+#define RCC_CFGR_PPRE_DIV_NONE 0
+#define RCC_CFGR_PPRE_DIV_2 (0b100)
+
+
+#define RCC_CFGR_PPRE2_BIT 13
+#define RCC_CFGR_PPRE2_MASK (0b111)
+
+
+#define RCC_CFGR_PPRE1_BIT 10
+#define RCC_CFGR_PPRE1_MASK (0b111)
+
+
+#define RCC_CFGR_HPRE_DIV_NONE 0
+
+#define RCC_CFGR_HPRE_BIT 4
+#define RCC_CFGR_HPRE_MASK (0b1111)
+
+
+#define RCC_CFGR_SWS_PLL (0b10)
+
+#define RCC_CFGR_SWS_BIT 2
+#define RCC_CFGR_SWS_MASK (0b11)
+
+
+#define RCC_CFGR_SW_PLL (0b10)
+
+#define RCC_CFGR_SW_BIT 0
+#define RCC_CFGR_SW_MASK (0b11)
+#define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT)
+
+
+
+#define RCC_AHB1ENR_GPIOAEN_BIT 0
+#define RCC_AHB1ENR_GPIOAEN_ENABLE (1 << RCC_AHB1ENR_GPIOAEN_BIT)
+
+
+#define RCC_APB1ENR_PWREN_BIT 28
+#define RCC_APB1ENR_PWREN_CLOCK_ENABLE (1 << RCC_APB1ENR_PWREN_BIT)
+
+#define RCC_APB1ENR_USART2EN_BIT 17
+#define RCC_APB1ENR_USART2EN_ENABLE (1 << RCC_APB1ENR_USART2EN_BIT)
+
+#define RCC_APB1ENR_TIM4_BIT 2
+#define RCC_APB1ENR_TIM4_ENABLE (1 << RCC_APB1ENR_TIM4_BIT)
+# 5 "src/main.c" 2
 # 1 "src/gpio.h" 1
 
 #define GPIO_H_ 
 
-# 1 "/nix/store/yr89i11mszv2az19r26l372zgaiivj1c-gcc-arm-embedded-12.3.rel1/lib/gcc/arm-none-eabi/12.3.1/include/stdbool.h" 1 3 4
-# 29 "/nix/store/yr89i11mszv2az19r26l372zgaiivj1c-gcc-arm-embedded-12.3.rel1/lib/gcc/arm-none-eabi/12.3.1/include/stdbool.h" 3 4
-#define _STDBOOL_H 
 
 
 
-#define bool _Bool
-
-#define true ((_Bool)+1u)
-#define false ((_Bool)+0u)
-# 50 "/nix/store/yr89i11mszv2az19r26l372zgaiivj1c-gcc-arm-embedded-12.3.rel1/lib/gcc/arm-none-eabi/12.3.1/include/stdbool.h" 3 4
-#define __bool_true_false_are_defined 1
-# 5 "src/gpio.h" 2
-
-
 struct gpio {
   volatile uint32_t MODER;
   volatile uint32_t OTYPER;
@@ -2033,10 +2127,36 @@ struct gpio {
   volatile uint32_t ODR;
   volatile uint32_t BSRR;
   volatile uint32_t LCKR;
-  volatile uint32_t AFRL[2];
+  volatile uint32_t AFRL;
-  volatile uint32_t AFRH[2];
+  volatile uint32_t AFRH;
 };
 
+#define GPIOA_BASE_ADDR (0x40020000U)
+#define GPIOA ((struct gpio *) GPIOA_BASE_ADDR)
+
+
+#define GPIO_MODER_MODER3_BIT 7
+#define GPIO_MODER_MODER3_MASK (0b11)
+#define GPIO_MODER_MODER3_AF (0b10)
+
+#define GPIO_MODER_MODER2_BIT 4
+#define GPIO_MODER_MODER2_MASK (0b11)
+#define GPIO_MODER_MODER2_AF (0b10)
+
+
+#define GPIO_AFRL_AFRL3_BIT 12
+#define GPIO_AFRL_AFRL3_MASK (0b1111)
+#define GPIO_AFRL_AFRL3_USART2_RX (0b0111)
+
+#define GPIO_AFRL_AFRL2_BIT 8
+#define GPIO_AFRL_AFRL2_MASK (0b1111)
+#define GPIO_AFRL_AFRL2_USART2_TX (0b0111)
+
+
+
+
+
+
 #define GPIO_BASE_ADDR (0x40020000U)
 #define GPIO_PORT_OFFSET (0x400U)
 #define GPIO(port) ((struct gpio*)(uintptr_t)(GPIO_BASE_ADDR + (GPIO_PORT_OFFSET * port)))
@@ -2058,35 +2178,260 @@ typedef enum {
 
 void gpio_set_mode(uint16_t pin, GPIO_MODE mode);
 void gpio_write(uint16_t pin, 
-# 40 "src/gpio.h" 3 4
+# 66 "src/gpio.h" 3 4
                              _Bool 
-# 40 "src/gpio.h"
+# 66 "src/gpio.h"
                                   val);
-# 4 "src/main.c" 2
+# 6 "src/main.c" 2
+# 1 "src/flash.h" 1
+
+#define FLASH_H_ 
+
+
+
+struct flash {
+  volatile uint32_t ACR;
+  volatile uint32_t KEYR;
+  volatile uint32_t OPTKEYR;
+  volatile uint32_t SR;
+  volatile uint32_t CR;
+  volatile uint32_t OPTCR;
+};
+
+#define FLASH_BASE_ADDR (0x40023C00U)
+#define FLASH ((struct flash *) FLASH_BASE_ADDR)
+
+
+
+#define FLASH_ACR_DCEN_BIT 10
+#define FLASH_ACR_DCEN_ENABLE (1 <<FLASH_ACR_DCEN_BIT)
+
+
+#define FLASH_ACR_ICEN_BIT 9
+#define FLASH_ACR_ICEN_ENABLE (1 <<FLASH_ACR_ICEN_BIT)
+
+
+#define FLASH_ACR_LATENCY_3_WAIT_STATES (0x0111)
+
+#define FLASH_ACR_LATENCY_BIT 0
+#define FLASH_ACR_LATENCY_MASK (0b1111)
+#define FLASH_ACR_LATENCY(latency) ((latency & FLASH_ACR_LATENCY_MASK) << FLASH_ACR_LATENCY_BIT)
+# 7 "src/main.c" 2
+# 1 "src/pwr.h" 1
+
+#define PWR_H_ 
+
+
+
+struct pwr {
+  volatile uint32_t CR;
+  volatile uint32_t CSR;
+};
+
+#define PWR_BASE_ADDR (0x40007000U)
+#define PWR ((struct pwr *) PWR_BASE_ADDR)
+
+
+#define PWR_SCALE3 (0b11)
+
+
+#define PWR_CR_VOS_BIT 14
+#define PWR_CR_VOS_MASK (0b11)
+#define PWR_CR_VOS(scale) ((scale & PWR_CR_VOS_MASK) << PWR_CR_VOS_BIT)
+# 8 "src/main.c" 2
+# 1 "src/timer.h" 1
+
+#define TIMER_H_ 
+
+
+
+struct timer {
+  volatile uint32_t CR1;
+  volatile uint32_t CR2;
+  volatile uint32_t SMCR;
+  volatile uint32_t DIER;
+  volatile uint32_t SR;
+  volatile uint32_t EGR;
+  volatile uint32_t CCMR1;
+  volatile uint32_t CCMR2;
+  volatile uint32_t CCER;
+  volatile uint32_t CNT;
+  volatile uint32_t PSC;
+  volatile uint32_t ARR;
+  volatile uint32_t RCR;
+  volatile uint32_t CCR1;
+  volatile uint32_t CCR2;
+  volatile uint32_t CCR3;
+  volatile uint32_t CCR4;
+  volatile uint32_t BDTR;
+  volatile uint32_t DCR;
+  volatile uint32_t DMAR;
+};
+
+#define TIM4_BASE_ADDR (0x40000800U)
+#define TIM4 ((struct timer *) TIM4_BASE_ADDR)
+
+#define TIM_CR1_CEN_BIT 0
+#define TIM_ENABLE (1 << TIM_CR1_CEN_BIT)
+
+void tim4_init(void);
+void tim4_start(void);
+# 9 "src/main.c" 2
+# 1 "src/usart.h" 1
+
+#define USART_H_ 
+
+
+
+struct usart {
+  volatile uint32_t SR;
+  volatile uint32_t DR;
+  volatile uint32_t BRR;
+  volatile uint32_t CR1;
+  volatile uint32_t CR2;
+  volatile uint32_t CR3;
+  volatile uint32_t GTPR;
+};
+
+#define USART2_BASE_ADDR (0x40004400U)
+#define USART2 ((struct usart *) USART2_BASE_ADDR)
+
+
+
+#define USART_SR_TXE_BIT 7
+#define USART_SR_TXE_TRANSMITTED (1 << USART_SR_TXE_BIT)
+
+
+#define USART_SR_RXNE_BIT 5
+#define USART_SR_RXNE_READY (1 <<USART_SR_RXNE_BIT)
+
+
+
+#define USART_CR1_OVER8_BIT 15
+#define USART_CR1_OVER8_8 (1 << USART_CR1_OVER8_BIT)
+
+
+#define USART_CR1_UE_BIT 13
+#define USART_CR1_UE_ENABLE (1 << USART_CR1_UE_BIT)
+
+
+#define USART_CR1_TE_BIT 3
+#define USART_CR1_TE_ENABLE (1 << USART_CR1_TE_BIT)
+
+
+#define USART_CR1_RE_BIT 2
+#define USART_CR1_RE_ENABLE (1 << USART_CR1_RE_BIT)
+
+
+#define USART_BRR_MANTISSA_BIT 4
+#define USART_BRR_MANTISSA_MASK (0b111111111111)
+
+#define USART_BRR_FRACTION_BIT 0
+#define USART_BRR_FRACTION_MASK (0b111)
+
+void usart2_init(void);
+void usart2_start(void);
+
+void usart2_write_byte(char byte);
+# 10 "src/main.c" 2
 
 #define exit 42
 
-static inline void spin(volatile uint32_t count) {
+static void system_clock_init(void) {
-  while (count--) (void) 0;
+
+  ((struct rcc *) (0x40023800U))->APB1ENR |= (1 << 28);
+
+
+  ((struct pwr *) (0x40007000U))->CR &= ~((0b11) << 14);
+  ((struct pwr *) (0x40007000U))->CR |= ((0b11) << 14);
+
+
+  ((struct rcc *) (0x40023800U))->CR |= (1 << 16);
+
+
+
+  while (!(((struct rcc *) (0x40023800U))->CR & (1 << 17)));
+
+
+
+  ((struct rcc *) (0x40023800U))->CR &= ~(1 << 24);
+
+
+  ((struct rcc *) (0x40023800U))->PLLCFGR |= (1 << 22);
+
+
+  ((struct rcc *) (0x40023800U))->PLLCFGR |= ((25 & (0b111111)) << 0) | ((196 & (0b111111111)) << 6) | ((2 & (0b11)) << 16) | ((4 & (0b1111)) << 24);
+
+
+  ((struct rcc *) (0x40023800U))->CFGR &= ~((0b1111) << 4);
+  ((struct rcc *) (0x40023800U))->CFGR |= (0 << 4);
+
+
+  ((struct rcc *) (0x40023800U))->CFGR &= ~((0b111) << 10);
+  ((struct rcc *) (0x40023800U))->CFGR |= ((0b100) << 10);
+
+
+  ((struct rcc *) (0x40023800U))->CFGR &= ~((0b111) << 13);
+  ((struct rcc *) (0x40023800U))->CFGR |= (0 << 13);
+
+
+  ((struct rcc *) (0x40023800U))->CR |= (1 << 24);
+
+
+
+  while (!(((struct rcc *) (0x40023800U))->CR & (1 << 17)));
+
+
+  ((struct flash *) (0x40023C00U))->ACR |= (1 <<10);
+  ((struct flash *) (0x40023C00U))->ACR |= (1 <<9);
+
+
+  ((struct flash *) (0x40023C00U))->ACR &= ~((0b1111) << 0);
+  ((struct rcc *) (0x40023800U))->CFGR |= ((0x0111) << 0);
+
+
+  ((struct rcc *) (0x40023800U))->CFGR &= ~((0b11) << 0);
+  ((struct rcc *) (0x40023800U))->CFGR |= ((0b10) << 0);
+
+
+
+  while (((((struct rcc *) (0x40023800U))->CFGR >> 2) & (0b11)) != (0b10));
+
+
+  ((struct rcc *) (0x40023800U))->CR &= ~(1 << 0);
 }
 
 int main(void) {
+  (void) system_clock_init();
+  (void) tim4_init();
+  (void) usart2_init();
+
+  (void) tim4_start();
+  (void) usart2_start();
+
   uint16_t led = (((('C') - 'A') << 8) | 13);
   ((struct rcc *) (0x40023800U))->AHB1ENR |= (1 << (led >> 8));
   gpio_set_mode(led, GPIO_MODE_OUTPUT);
-  for (;;) {
+
-    gpio_write(led, 
+  uint16_t counter = ((struct timer *) (0x40000800U))->CNT;
-# 16 "src/main.c" 3 4
+  
-                   ((_Bool)+1u)
+# 90 "src/main.c" 3 4
-# 16 "src/main.c"
+ _Bool 
-                       );
+# 90 "src/main.c"
-    spin(999999);
+      led_on = 
-    gpio_write(led, 
+# 90 "src/main.c" 3 4
-# 18 "src/main.c" 3 4
                ((_Bool)+0u)
-# 18 "src/main.c"
+# 90 "src/main.c"
-                        );
+                    ;
-    spin(999999);
+  while(1) {
+ if ((((struct timer *) (0x40000800U))->CNT - counter) >= 250) {
+  led_on = !led_on;
+  gpio_write(led, led_on);
+
+  usart2_write_byte('a');
+
+  counter = ((struct timer *) (0x40000800U))->CNT;
+ }
   };
 
   return 42;

flake.nix

@@ -16,7 +16,11 @@
 
         devShells = nixpkgs.lib.genAttrs systems (system:
           let
-            pkgs = nixpkgs.legacyPackages.${system};
+            # pkgs = nixpkgs.legacyPackages.${system};
+            pkgs = import nixpkgs {
+              inherit system;
+              config.allowUnfree = true;
+            };
           in
             {
               default = pkgs.mkShell {
@@ -24,6 +28,10 @@
                   pkgs.gnumake
                   pkgs.gcc-arm-embedded
                   pkgs.stlink
+                  pkgs.gdb
+                  pkgs.openocd
+                  pkgs.stm32cubemx
+                  pkgs.gdbgui
                 ];
               };
             }

src/flash.h

@@ -0,0 +1,34 @@
+#ifndef FLASH_H_
+#define FLASH_H_
+
+#include <inttypes.h>
+
+struct flash {
+  volatile uint32_t ACR;      // Flash access control register
+  volatile uint32_t KEYR;     // Flash key register
+  volatile uint32_t OPTKEYR;  // Flash option key register
+  volatile uint32_t SR;       // Flash status register
+  volatile uint32_t CR;       // Flash control register
+  volatile uint32_t OPTCR;    // Flash option control register
+};
+
+#define FLASH_BASE_ADDR (0x40023C00U)
+#define FLASH ((struct flash *) FLASH_BASE_ADDR)
+
+// ACR Register
+// Data cache enable
+#define FLASH_ACR_DCEN_BIT 10
+#define FLASH_ACR_DCEN_ENABLE (1 <<FLASH_ACR_DCEN_BIT)
+
+// Instruction cache enable
+#define FLASH_ACR_ICEN_BIT 9
+#define FLASH_ACR_ICEN_ENABLE (1 <<FLASH_ACR_ICEN_BIT)
+
+// Latency
+#define FLASH_ACR_LATENCY_3_WAIT_STATES (0x0111)
+
+#define FLASH_ACR_LATENCY_BIT 0 // Bits [3:0]
+#define FLASH_ACR_LATENCY_MASK (0b1111)
+#define FLASH_ACR_LATENCY(latency) ((latency & FLASH_ACR_LATENCY_MASK) << FLASH_ACR_LATENCY_BIT)
+
+#endif

src/gpio.h

@@ -13,10 +13,36 @@ struct gpio {
   volatile uint32_t ODR;      // Port output data register
   volatile uint32_t BSRR;     // Port bit set/reset register
   volatile uint32_t LCKR;     // Port configuration lock register
-  volatile uint32_t AFRL[2];  // Alternative function low register
+  volatile uint32_t AFRL;     // Alternative function low register
-  volatile uint32_t AFRH[2];  // Alternative function high register
+  volatile uint32_t AFRH;     // Alternative function high register
 };
 
+#define GPIOA_BASE_ADDR (0x40020000U)
+#define GPIOA ((struct gpio *) GPIOA_BASE_ADDR)
+
+// MODER register
+#define GPIO_MODER_MODER3_BIT 7 // Bits [7:6]
+#define GPIO_MODER_MODER3_MASK (0b11)
+#define GPIO_MODER_MODER3_AF (0b10)
+
+#define GPIO_MODER_MODER2_BIT 4 // Bits [5:4]
+#define GPIO_MODER_MODER2_MASK (0b11)
+#define GPIO_MODER_MODER2_AF (0b10)
+
+// AFRL register
+#define GPIO_AFRL_AFRL3_BIT 12 // Bits [15:12]
+#define GPIO_AFRL_AFRL3_MASK (0b1111)
+#define GPIO_AFRL_AFRL3_USART2_RX (0b0111) // Alternative function 7
+
+#define GPIO_AFRL_AFRL2_BIT 8 // Bits [11:8]
+#define GPIO_AFRL_AFRL2_MASK (0b1111)
+#define GPIO_AFRL_AFRL2_USART2_TX (0b0111) // Alternative function 7
+
+
+
+
+
+
 #define GPIO_BASE_ADDR (0x40020000U)
 #define GPIO_PORT_OFFSET (0x400U)
 #define GPIO(port) ((struct gpio*)(uintptr_t)(GPIO_BASE_ADDR + (GPIO_PORT_OFFSET * port)))

src/main.c

@@ -1,22 +1,102 @@
 #include <inttypes.h>
+#include <stdbool.h>
+
 #include "rcc.h"
 #include "gpio.h"
+#include "flash.h"
+#include "pwr.h"
+#include "timer.h"
+#include "usart.h"
 
 #define exit 42
 
-static inline void spin(volatile uint32_t count) {
+static void system_clock_init(void) {
-  while (count--) (void) 0;
+  // Power on clock for PLL
+  RCC->APB1ENR |= RCC_APB1ENR_PWREN_CLOCK_ENABLE;
+
+  // Set voltage scaling to "high"
+  PWR->CR &= ~(PWR_CR_VOS_MASK << PWR_CR_VOS_BIT);
+  PWR->CR |= (PWR_SCALE3 << PWR_CR_VOS_BIT);
+
+  // Turn on HSE
+  RCC->CR |= RCC_CR_HSEON_ON;
+
+  // Wait indefinitely for HSE to be ready
+  // TODO indicate error/timeout somehow?
+  while (!(RCC->CR & RCC_CR_HSERDY_READY));
+
+  // Disable PLL before changing settings as documentation state
+  // "These bits should be written only if PLL is disabled."
+  RCC->CR &= ~RCC_CR_PLLON_ON;
+
+  // Set HSE as PLL source
+  RCC->PLLCFGR |= RCC_PLLCFGR_PLLSRC_HSE;
+
+  // Settings to achieve system clock of 96Mhz
+  RCC->PLLCFGR |= RCC_PLLCFGR_PLLM(25) | RCC_PLLCFGR_PLLN(196) | RCC_PLLCFGR_PLLP(2) | RCC_PLLCFGR_PLLQ(4);
+
+  // Set AHB prescalar to /1
+  RCC->CFGR &= ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_BIT);
+  RCC->CFGR |= (RCC_CFGR_HPRE_DIV_NONE << RCC_CFGR_HPRE_BIT);
+
+  // Set APB1 prescalar to /2
+  RCC->CFGR &= ~(RCC_CFGR_PPRE1_MASK << RCC_CFGR_PPRE1_BIT);
+  RCC->CFGR |= (RCC_CFGR_PPRE_DIV_2 << RCC_CFGR_PPRE1_BIT);
+
+  // Set APB2 prescalar to /1
+  RCC->CFGR &= ~(RCC_CFGR_PPRE2_MASK << RCC_CFGR_PPRE2_BIT);
+  RCC->CFGR |= (RCC_CFGR_PPRE_DIV_NONE << RCC_CFGR_PPRE2_BIT);
+
+  // Turn PLL back on
+  RCC->CR |= RCC_CR_PLLON_ON;
+
+  // Wait indefinitely for PLL to be ready
+  // TODO indicate error/timeout somehow?
+  while (!(RCC->CR & RCC_CR_HSERDY_READY));
+
+  // Enable caching of instructions and data
+  FLASH->ACR |= FLASH_ACR_DCEN_ENABLE;
+  FLASH->ACR |= FLASH_ACR_ICEN_ENABLE;
+
+  // Set latency to be 3 wait states (TODO: understand why exactly 3)
+  FLASH->ACR &= ~(FLASH_ACR_LATENCY_MASK << FLASH_ACR_LATENCY_BIT);
+  RCC->CFGR |= (FLASH_ACR_LATENCY_3_WAIT_STATES << FLASH_ACR_LATENCY_BIT);
+
+  // Use PLL as system clock
+  RCC->CFGR &= ~(RCC_CFGR_SW_MASK << RCC_CFGR_SW_BIT);
+  RCC->CFGR |= (RCC_CFGR_SW_PLL << RCC_CFGR_SW_BIT);
+
+  // Wait indefinitely for PLL clock to be selected
+  // TODO indicate error/timeout somehow?
+  while (((RCC->CFGR >> RCC_CFGR_SWS_BIT) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL);
+
+  // Turn off HSI (which is on by default)
+  RCC->CR &= ~RCC_CR_HSION_ON;
 }
 
 int main(void) {
+  (void) system_clock_init();
+  (void) tim4_init();
+  (void) usart2_init();
+
+  (void) tim4_start();
+  (void) usart2_start();
+
   uint16_t led = PIN('C', 13);           // Blue LED
   RCC->AHB1ENR |= BIT(PINPORT(led));     // Enable GPIO clock for LED
   gpio_set_mode(led, GPIO_MODE_OUTPUT);  // Set blue LED to output mode
-  for (;;) {
+
-    gpio_write(led, true);
+  uint16_t counter = TIM4->CNT;
-    spin(999999);
+  bool led_on = false;
-    gpio_write(led, false);
+  while(1) {
-    spin(999999);
+	if ((TIM4->CNT - counter) >= 250) {
+	 led_on = !led_on;
+	 gpio_write(led, led_on);
+
+	 usart2_write_byte('a');
+
+	 counter = TIM4->CNT;
+	}
   };
 
   return exit;

src/pwr.h

@@ -0,0 +1,22 @@
+#ifndef PWR_H_
+#define PWR_H_
+
+#include <inttypes.h>
+
+struct pwr {
+  volatile uint32_t CR;   // Power control register
+  volatile uint32_t CSR;  // Power control/status registe
+};
+
+#define PWR_BASE_ADDR (0x40007000U)
+#define PWR ((struct pwr *) PWR_BASE_ADDR)
+
+// Power control register
+#define PWR_SCALE3 (0b11)
+
+// Regulator voltage scaling output selection
+#define PWR_CR_VOS_BIT 14 // Bits [15:14]
+#define PWR_CR_VOS_MASK (0b11)
+#define PWR_CR_VOS(scale) ((scale & PWR_CR_VOS_MASK) << PWR_CR_VOS_BIT)
+
+#endif

src/rcc.h

@@ -37,4 +37,96 @@ struct rcc {
 #define RCC_BASE_ADDR (0x40023800U)
 #define RCC ((struct rcc *) RCC_BASE_ADDR)
 
+// CR Register
+// PLL ready flag
+#define RCC_CR_PLLRDY_BIT 25
+#define RCC_CR_PLLRDY_LOCKED (1 << RCC_CR_PLLRDY_BIT)
+
+// PLL toggle
+#define RCC_CR_PLLON_BIT 24
+#define RCC_CR_PLLON_ON  (1 << RCC_CR_PLLON_BIT)
+
+// HSE clock ready flag
+#define RCC_CR_HSERDY_BIT 17
+#define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT)
+
+// HSE clock enable
+#define RCC_CR_HSEON_BIT 16
+#define RCC_CR_HSEON_ON (1 << RCC_CR_HSEON_BIT)
+
+// HSI clock ready flag
+#define RCC_CR_HSIRDY_BIT 1
+#define RCC_CR_HSIRDY_READY (1 << RCC_CR_HSIRDY_BIT)
+
+// HSI clock enable
+#define RCC_CR_HSION_BIT 0
+#define RCC_CR_HSION_ON  (1 << RCC_CR_HSION_BIT)
+
+// PLLCFGR Register
+#define RCC_PLLCFGR_PLLQ_BIT 24 // Bits [27:24]
+#define RCC_PLLCFGR_PLLQ_MASK (0b1111)
+#define RCC_PLLCFGR_PLLQ(q) ((q & RCC_PLLCFGR_PLLQ_MASK) << RCC_PLLCFGR_PLLQ_BIT)
+
+#define RCC_PLLCFGR_PLLSRC_BIT 22
+#define RCC_PLLCFGR_PLLSRC_HSE (1 << RCC_PLLCFGR_PLLSRC_BIT)
+
+#define RCC_PLLCFGR_PLLP_BIT 16 // Bits [17:16]
+#define RCC_PLLCFGR_PLLP_MASK (0b11)
+#define RCC_PLLCFGR_PLLP(p) ((p & RCC_PLLCFGR_PLLP_MASK) << RCC_PLLCFGR_PLLP_BIT)
+
+#define RCC_PLLCFGR_PLLN_BIT 6 // Bits [14:6]
+#define RCC_PLLCFGR_PLLN_MASK (0b111111111)
+#define RCC_PLLCFGR_PLLN(n) ((n & RCC_PLLCFGR_PLLN_MASK) << RCC_PLLCFGR_PLLN_BIT)
+
+#define RCC_PLLCFGR_PLLM_BIT 0 // Bits [5:0]
+#define RCC_PLLCFGR_PLLM_MASK (0b111111)
+#define RCC_PLLCFGR_PLLM(m) ((m & RCC_PLLCFGR_PLLM_MASK) << RCC_PLLCFGR_PLLM_BIT)
+
+// CFGR Register
+// APB{1,2} prescalar
+#define RCC_CFGR_PPRE_DIV_NONE	0
+#define RCC_CFGR_PPRE_DIV_2	(0b100)
+
+// APB2
+#define RCC_CFGR_PPRE2_BIT 13 // Bits [15:13]
+#define RCC_CFGR_PPRE2_MASK (0b111)
+
+// APB1
+#define RCC_CFGR_PPRE1_BIT 10 // Bits [12:10]
+#define RCC_CFGR_PPRE1_MASK (0b111)
+
+// AHB prescalar
+#define RCC_CFGR_HPRE_DIV_NONE 0
+
+#define RCC_CFGR_HPRE_BIT 4 // Bits [7:4]
+#define RCC_CFGR_HPRE_MASK (0b1111)
+
+//System clock switch status
+#define RCC_CFGR_SWS_PLL (0b10)
+
+#define RCC_CFGR_SWS_BIT 2 // Bits [3:2]
+#define RCC_CFGR_SWS_MASK (0b11)
+
+// System clock switch
+#define RCC_CFGR_SW_PLL (0b10)
+
+#define RCC_CFGR_SW_BIT 0 // Bits [1:0]
+#define RCC_CFGR_SW_MASK (0b11)
+#define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT)
+
+// AHB1ENR Register
+// GPIOA AHB1ENR
+#define RCC_AHB1ENR_GPIOAEN_BIT 0
+#define RCC_AHB1ENR_GPIOAEN_ENABLE (1 << RCC_AHB1ENR_GPIOAEN_BIT)
+
+// APB1ENR Register
+#define RCC_APB1ENR_PWREN_BIT 28
+#define RCC_APB1ENR_PWREN_CLOCK_ENABLE (1 << RCC_APB1ENR_PWREN_BIT)
+
+#define RCC_APB1ENR_USART2EN_BIT 17
+#define RCC_APB1ENR_USART2EN_ENABLE (1 << RCC_APB1ENR_USART2EN_BIT)
+
+#define RCC_APB1ENR_TIM4_BIT 2
+#define RCC_APB1ENR_TIM4_ENABLE (1 << RCC_APB1ENR_TIM4_BIT)
+
 #endif

src/timer.c

@@ -0,0 +1,22 @@
+#include "rcc.h"
+#include "timer.h"
+
+void tim4_init(void) {
+  // Enable timer
+  RCC->APB1ENR |= RCC_APB1ENR_TIM4_ENABLE;
+
+  // Reset timer
+  TIM4->CR1 = 0x0000;
+  TIM4->CR2 = 0x0000;
+
+  // Set prescaler
+  // f_clk = 48MHz -> /48000 = 1KHz counting frequency = 1ms
+  TIM4->PSC = (uint16_t) 48000 - 1;
+
+  // Set ARR to maximum value to get 1ms between updates
+  TIM4->ARR = (uint16_t) 0xFFFF;
+}
+
+void tim4_start(void) {
+  TIM4->CR1 |= TIM_ENABLE;
+}

src/timer.h

@@ -0,0 +1,38 @@
+#ifndef TIMER_H_
+#define TIMER_H_
+
+#include <inttypes.h>
+
+struct timer {
+  volatile uint32_t CR1;    // Control register 1
+  volatile uint32_t CR2;    // Control register 2
+  volatile uint32_t SMCR;   // Slave mode control register
+  volatile uint32_t DIER;   // DMA/interrupt enable registe
+  volatile uint32_t SR;     // Status register
+  volatile uint32_t EGR;    // Event generation register
+  volatile uint32_t CCMR1;  // Capture/compare mode register 1
+  volatile uint32_t CCMR2;  // Capture/compare mode register 2
+  volatile uint32_t CCER;   // Capture/compare enable register
+  volatile uint32_t CNT;    // Counter
+  volatile uint32_t PSC;    // Prescalar
+  volatile uint32_t ARR;    // Auto-reload register
+  volatile uint32_t RCR;    // Repetition counter registe
+  volatile uint32_t CCR1;   // Capture/compare register 1
+  volatile uint32_t CCR2;   // Capture/compare register 2
+  volatile uint32_t CCR3;   // Capture/compare register 3
+  volatile uint32_t CCR4;   // Capture/compare register 4
+  volatile uint32_t BDTR;   // Break and dead-time register
+  volatile uint32_t DCR;    // DMA control register
+  volatile uint32_t DMAR;   // DMA address for full transfer
+};
+
+#define TIM4_BASE_ADDR (0x40000800U)
+#define TIM4 ((struct timer *) TIM4_BASE_ADDR)
+
+#define TIM_CR1_CEN_BIT 0
+#define TIM_ENABLE (1 << TIM_CR1_CEN_BIT)
+
+void tim4_init(void);
+void tim4_start(void);
+
+#endif

src/usart.c

@@ -0,0 +1,71 @@
+#include "rcc.h"
+#include "gpio.h"
+#include "usart.h"
+
+void usart2_init(void) {
+  // Enable clock for GPIOA
+  RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN_ENABLE;
+
+  // Configure PA2 and PA3 (USART2 pins) to use alternative functions
+  GPIOA->MODER &= ~(GPIO_MODER_MODER2_MASK << GPIO_MODER_MODER2_BIT);
+  GPIOA->MODER |= (GPIO_MODER_MODER2_AF << GPIO_MODER_MODER2_BIT);
+  GPIOA->MODER &= ~(GPIO_MODER_MODER3_MASK << GPIO_MODER_MODER3_BIT);
+  GPIOA->MODER |= (GPIO_MODER_MODER3_AF << GPIO_MODER_MODER3_BIT);
+
+  // Set pin alternative modes to use USART
+  GPIOA->AFRL &= ~(GPIO_AFRL_AFRL2_MASK << GPIO_AFRL_AFRL2_BIT);
+  GPIOA->AFRL |= (GPIO_AFRL_AFRL2_USART2_TX << GPIO_AFRL_AFRL2_BIT);
+  GPIOA->AFRL &= ~(GPIO_AFRL_AFRL3_MASK << GPIO_AFRL_AFRL3_BIT);
+  GPIOA->AFRL |= (GPIO_AFRL_AFRL3_USART2_RX << GPIO_AFRL_AFRL3_BIT);
+
+  // Enable USART
+  RCC->AHB1ENR |= RCC_APB1ENR_USART2EN_ENABLE;
+
+  // Clear control registers
+  USART2->CR1 = 0;
+  USART2->CR2 = 0;
+  USART2->CR3 = 0;
+
+  // Calculate Baud rate:
+  // baud = f_clock / (8 * (2 - OVER8) * USARTDIV); =>
+  // (8 * (2 - OVER8) * USARTDIV) = f_clock / baud; =>
+  // USARTDIV = (f_clock / (baud * (8 * (2 - OVER8))); =>
+
+  // Target Baud rate = 115200, f_clock = 48MHz
+
+  // With OVER8 = 1 (oversampling by 8)
+  // USARTDIV = (48E6 / (115200 * (8 * (2 - 1))) = 52.083
+  // mantissa = 52
+  // fraction = 0.083 * 8 = 0.664 ~= 1
+
+  // rounding fraction up: USARTDIV = 53
+  // baud = 48E6 / (8 * (52 + 1)) = 113207.54716981133
+  // error of 0.1% (115200 / 113207.54716981133)
+
+  // rounding fraction down: USARTDIV = 52
+  // baud = 48E6 / (8 * 52) = 115384.61538461539
+  // error of 0.001% (115384.61538461539 / 115200)
+
+  USART2->CR1 |= USART_CR1_OVER8_8;
+
+  USART2->BRR &= ~(USART_BRR_MANTISSA_MASK << USART_BRR_MANTISSA_BIT);
+  USART2->BRR |= (0x34 << USART_BRR_MANTISSA_BIT);
+  USART2->BRR &= ~(USART_BRR_FRACTION_MASK << USART_BRR_FRACTION_BIT);
+  USART2->BRR |= (0x0 << USART_BRR_FRACTION_BIT);
+
+  // Enable transmitter and receiver
+  USART2->CR1 |= USART_CR1_TE_ENABLE;
+  USART2->CR1 |= USART_CR1_RE_ENABLE;
+}
+
+void usart2_start(void) {
+  USART2->CR1 |= USART_CR1_UE_ENABLE;
+}
+
+void usart2_write_byte(char c) {
+  // Send data
+  USART2->DR = c;
+
+  // Wait indefinitely for transmission to be ready for data
+  while ((USART2->SR & USART_SR_TXE_TRANSMITTED) == 0);
+}

src/usart.h

@@ -0,0 +1,57 @@
+#ifndef USART_H_
+#define USART_H_
+
+#include <inttypes.h>
+
+struct usart {
+  volatile uint32_t SR;   // Status register
+  volatile uint32_t DR;   // Data register
+  volatile uint32_t BRR;  // Baud rate register
+  volatile uint32_t CR1;  // Control register 1
+  volatile uint32_t CR2;  // Control register 2
+  volatile uint32_t CR3;  // Control register 3
+  volatile uint32_t GTPR; // Guard time and prescaler registe
+};
+
+#define USART2_BASE_ADDR (0x40004400U)
+#define USART2 ((struct usart *) USART2_BASE_ADDR)
+
+// SR Register
+// Transmission data register empty
+#define USART_SR_TXE_BIT 7
+#define USART_SR_TXE_TRANSMITTED (1 << USART_SR_TXE_BIT)
+
+// Read data register not empty
+#define USART_SR_RXNE_BIT 5
+#define USART_SR_RXNE_READY (1 <<USART_SR_RXNE_BIT)
+
+// CR Register
+// Oversampling mode
+#define USART_CR1_OVER8_BIT 15
+#define USART_CR1_OVER8_8 (1 << USART_CR1_OVER8_BIT)
+
+// USART enable
+#define USART_CR1_UE_BIT 13
+#define USART_CR1_UE_ENABLE (1 << USART_CR1_UE_BIT)
+
+// Trasmitter enable
+#define USART_CR1_TE_BIT 3
+#define USART_CR1_TE_ENABLE (1 << USART_CR1_TE_BIT)
+
+// Receiver enable
+#define USART_CR1_RE_BIT 2
+#define USART_CR1_RE_ENABLE (1 << USART_CR1_RE_BIT)
+
+// BRR Register
+#define USART_BRR_MANTISSA_BIT 4 // Bits [15:4]
+#define USART_BRR_MANTISSA_MASK (0b111111111111) // Bits [15:4]
+
+#define USART_BRR_FRACTION_BIT 0 // Bits [3:0]
+#define USART_BRR_FRACTION_MASK (0b111) // Bits [3:0]
+
+void usart2_init(void);
+void usart2_start(void);
+
+void usart2_write_byte(char byte);
+
+#endif

stlink.cfg

@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# STMicroelectronics ST-LINK/V1, ST-LINK/V2, ST-LINK/V2-1, STLINK-V3 in-circuit
+# debugger/programmer
+#
+
+adapter driver hla
+hla_layout stlink
+hla_device_desc "ST-LINK"
+hla_vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753 0x0483 0x3754
+
+# Optionally specify the serial number of ST-LINK/V2 usb device.  ST-LINK/V2
+# devices seem to have serial numbers with unreadable characters.  ST-LINK/V2
+# firmware version >= V2.J21.S4 recommended to avoid issues with adapter serial
+# number reset issues.
+# eg.
+# adapter serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f"

stm32f4x.cfg

@@ -0,0 +1,148 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32f4x family
+
+#
+# stm32f4 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32f4x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 32kB (Available RAM in smallest device STM32F410)
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x8000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      # See STM Document RM0090
+      # Section 38.6.3 - corresponds to Cortex-M4 r0p1
+      set _CPUTAPID 0x4ba00477
+   } {
+      set _CPUTAPID 0x2ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+   jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
+
+flash bank $_CHIPNAME.otp stm32f2x 0x1fff7800 0 0 0 $_TARGETNAME
+
+if { [info exists QUADSPI] && $QUADSPI } {
+   set a [llength [flash list]]
+   set _QSPINAME $_CHIPNAME.qspi
+   flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
+}
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
+#
+# Since we may be running of an RC oscilator, we crank down the speed a
+# bit more to be on the safe side. Perhaps superstition, but if are
+# running off a crystal, we can run closer to the limit. Note
+# that there can be a pretty wide band where things are more or less stable.
+adapter speed 2000
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event examine-end {
+	# Enable debug during low power modes (uses more power)
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0xE0042004 0x00000007 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0xE0042008 0x00001800 0
+}
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_chipname} {
+	targets $_chipname.cpu
+
+	if { [$_chipname.tpiu cget -protocol] eq "sync" } {
+		switch [$_chipname.tpiu cget -port-width] {
+			1 {
+				# Set TRACE_IOEN; TRACE_MODE to sync 1 bit; GPIOE[2-3] to AF0
+				mmw 0xE0042004 0x00000060 0x000000c0
+				mmw 0x40021020 0x00000000 0x0000ff00
+				mmw 0x40021000 0x000000a0 0x000000f0
+				mmw 0x40021008 0x000000f0 0x00000000
+			  }
+			2 {
+				# Set TRACE_IOEN; TRACE_MODE to sync 2 bit; GPIOE[2-4] to AF0
+				mmw 0xE0042004 0x000000a0 0x000000c0
+				mmw 0x40021020 0x00000000 0x000fff00
+				mmw 0x40021000 0x000002a0 0x000003f0
+				mmw 0x40021008 0x000003f0 0x00000000
+			  }
+			4 {
+				# Set TRACE_IOEN; TRACE_MODE to sync 4 bit; GPIOE[2-6] to AF0
+				mmw 0xE0042004 0x000000e0 0x000000c0
+				mmw 0x40021020 0x00000000 0x0fffff00
+				mmw 0x40021000 0x00002aa0 0x00003ff0
+				mmw 0x40021008 0x00003ff0 0x00000000
+			  }
+		}
+	} else {
+		# Set TRACE_IOEN; TRACE_MODE to async
+		mmw 0xE0042004 0x00000020 0x000000c0
+	}
+}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_CHIPNAME"
+
+$_TARGETNAME configure -event reset-init {
+	# Configure PLL to boost clock to HSI x 4 (64 MHz)
+	mww 0x40023804 0x08012008   ;# RCC_PLLCFGR 16 Mhz /8 (M) * 128 (N) /4(P)
+	mww 0x40023C00 0x00000102   ;# FLASH_ACR = PRFTBE | 2(Latency)
+	mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON
+	sleep 10                    ;# Wait for PLL to lock
+	mmw 0x40023808 0x00001000 0 ;# RCC_CFGR |= RCC_CFGR_PPRE1_DIV2
+	mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
+
+	# Boost JTAG frequency
+	adapter speed 8000
+}
+
+$_TARGETNAME configure -event reset-start {
+	# Reduce speed since CPU speed will slow down to 16MHz with the reset
+	adapter speed 2000
+}

todo.txt

@@ -0,0 +1,2 @@
+- implement UART
+- implement tim4 interrupt