wip

build/final.elf.map

@@ -128,9 +128,9 @@ Discarded input sections
  .debug_macro   0x00000000      0x1df build/usart.o
  .debug_macro   0x00000000       0x89 build/usart.o
  .debug_macro   0x00000000      0x4cc build/usart.o
- .debug_macro   0x00000000      0x167 build/usart.o
+ .debug_macro   0x00000000      0x198 build/usart.o
  .debug_macro   0x00000000       0x22 build/usart.o
- .debug_macro   0x00000000       0x5e build/usart.o
+ .debug_macro   0x00000000       0x76 build/usart.o
 
 Memory Configuration
 
@@ -157,7 +157,7 @@ LOAD build/usart.o
                 0x08000000                interrupt_vector_table
                 0x08000198                        . = ALIGN (0x4)
 
-.text           0x08000198      0x520
+.text           0x08000198      0x574
                 0x08000198                        . = ALIGN (0x4)
  *(.text)
  *(.text.*)
@@ -172,129 +172,129 @@ LOAD build/usart.o
                 0x08000292                gpio_write
  *fill*         0x080002de        0x2 
  .text.system_clock_init
-                0x080002e0      0x11c build/main.o
- .text.main     0x080003fc       0x9c build/main.o
-                0x080003fc                main
+                0x080002e0      0x128 build/main.o
+ .text.main     0x08000408       0x9c build/main.o
+                0x08000408                main
  .text.init_memory
-                0x08000498       0x64 build/startup.o
-                0x08000498                init_memory
- .text.reset    0x080004fc       0x10 build/startup.o
-                0x080004fc                reset
+                0x080004a4       0x64 build/startup.o
+                0x080004a4                init_memory
+ .text.reset    0x08000508       0x10 build/startup.o
+                0x08000508                reset
  .text.default_handler
-                0x0800050c        0x8 build/startup.o
-                0x0800050c                exti0
-                0x0800050c                debug_monitor
-                0x0800050c                rcc
-                0x0800050c                x
-                0x0800050c                sdio
-                0x0800050c                usage_fault
-                0x0800050c                tim1_up_tim10
-                0x0800050c                usart1
-                0x0800050c                i2c3_er
-                0x0800050c                spi2
-                0x0800050c                dma1_stream1
-                0x0800050c                bus_fault
-                0x0800050c                spi5
-                0x0800050c                exti3
-                0x0800050c                dma2_stream5
-                0x0800050c                tim2
-                0x0800050c                dma1_stream6
-                0x0800050c                default_handler
-                0x0800050c                i2c1_er
-                0x0800050c                hard_fault
-                0x0800050c                usart6
-                0x0800050c                exti15_10
-                0x0800050c                usart2
-                0x0800050c                pend_sv
-                0x0800050c                i2c1_ev
-                0x0800050c                wwdg
-                0x0800050c                adc
-                0x0800050c                rtc_alarm
-                0x0800050c                spi3
-                0x0800050c                exti1
-                0x0800050c                mem_manage
-                0x0800050c                dma2_stream1
-                0x0800050c                dma1_stream2
-                0x0800050c                dma2_stream3
-                0x0800050c                sv_call
-                0x0800050c                tim3
-                0x0800050c                otg_fs
-                0x0800050c                dma1_stream5
-                0x0800050c                dma2_stream6
-                0x0800050c                flash
-                0x0800050c                tamp_stamp
-                0x0800050c                i2c3_ev
-                0x0800050c                rtc_wkup
-                0x0800050c                dma2_stream0
-                0x0800050c                pvd
-                0x0800050c                fpu
-                0x0800050c                exti4
-                0x0800050c                exti2
-                0x0800050c                spi1
-                0x0800050c                dma1_stream0
-                0x0800050c                tim1_brk_tim9
-                0x0800050c                i2c2_ev
-                0x0800050c                otg_fs_wkup
-                0x0800050c                spi4
-                0x0800050c                dma2_stream2
-                0x0800050c                tim1_cc
-                0x0800050c                tim1_trg_com_tim11
-                0x0800050c                exti9_5
-                0x0800050c                dma1_stream3
-                0x0800050c                dma2_stream4
-                0x0800050c                i2c2_er
-                0x0800050c                dma2_stream7
-                0x0800050c                dma1_stream7
-                0x0800050c                nmi
-                0x0800050c                systick
-                0x0800050c                tim4
-                0x0800050c                tim5
-                0x0800050c                dma1_stream4
+                0x08000518        0x8 build/startup.o
+                0x08000518                exti0
+                0x08000518                debug_monitor
+                0x08000518                rcc
+                0x08000518                x
+                0x08000518                sdio
+                0x08000518                usage_fault
+                0x08000518                tim1_up_tim10
+                0x08000518                usart1
+                0x08000518                i2c3_er
+                0x08000518                spi2
+                0x08000518                dma1_stream1
+                0x08000518                bus_fault
+                0x08000518                spi5
+                0x08000518                exti3
+                0x08000518                dma2_stream5
+                0x08000518                tim2
+                0x08000518                dma1_stream6
+                0x08000518                default_handler
+                0x08000518                i2c1_er
+                0x08000518                hard_fault
+                0x08000518                usart6
+                0x08000518                exti15_10
+                0x08000518                usart2
+                0x08000518                pend_sv
+                0x08000518                i2c1_ev
+                0x08000518                wwdg
+                0x08000518                adc
+                0x08000518                rtc_alarm
+                0x08000518                spi3
+                0x08000518                exti1
+                0x08000518                mem_manage
+                0x08000518                dma2_stream1
+                0x08000518                dma1_stream2
+                0x08000518                dma2_stream3
+                0x08000518                sv_call
+                0x08000518                tim3
+                0x08000518                otg_fs
+                0x08000518                dma1_stream5
+                0x08000518                dma2_stream6
+                0x08000518                flash
+                0x08000518                tamp_stamp
+                0x08000518                i2c3_ev
+                0x08000518                rtc_wkup
+                0x08000518                dma2_stream0
+                0x08000518                pvd
+                0x08000518                fpu
+                0x08000518                exti4
+                0x08000518                exti2
+                0x08000518                spi1
+                0x08000518                dma1_stream0
+                0x08000518                tim1_brk_tim9
+                0x08000518                i2c2_ev
+                0x08000518                otg_fs_wkup
+                0x08000518                spi4
+                0x08000518                dma2_stream2
+                0x08000518                tim1_cc
+                0x08000518                tim1_trg_com_tim11
+                0x08000518                exti9_5
+                0x08000518                dma1_stream3
+                0x08000518                dma2_stream4
+                0x08000518                i2c2_er
+                0x08000518                dma2_stream7
+                0x08000518                dma1_stream7
+                0x08000518                nmi
+                0x08000518                systick
+                0x08000518                tim4
+                0x08000518                tim5
+                0x08000518                dma1_stream4
  .text.tim4_init
-                0x08000514       0x40 build/timer.o
-                0x08000514                tim4_init
+                0x08000520       0x40 build/timer.o
+                0x08000520                tim4_init
  .text.tim4_start
-                0x08000554       0x20 build/timer.o
-                0x08000554                tim4_start
+                0x08000560       0x20 build/timer.o
+                0x08000560                tim4_start
  .text.usart2_init
-                0x08000574       0xb8 build/usart.o
-                0x08000574                usart2_init
+                0x08000580      0x100 build/usart.o
+                0x08000580                usart2_init
  .text.usart2_start
-                0x0800062c       0x20 build/usart.o
-                0x0800062c                usart2_start
+                0x08000680       0x20 build/usart.o
+                0x08000680                usart2_start
  .text.usart2_write_byte
-                0x0800064c       0x30 build/usart.o
-                0x0800064c                usart2_write_byte
+                0x080006a0       0x30 build/usart.o
+                0x080006a0                usart2_write_byte
  .text.usart2_write
-                0x0800067c       0x2a build/usart.o
-                0x0800067c                usart2_write
+                0x080006d0       0x2a build/usart.o
+                0x080006d0                usart2_write
  *(.rodata)
- *fill*         0x080006a6        0x2 
- .rodata        0x080006a8        0xf build/main.o
+ *fill*         0x080006fa        0x2 
+ .rodata        0x080006fc        0xf build/main.o
  *(.rodata.*)
-                0x080006b8                        . = ALIGN (0x4)
- *fill*         0x080006b7        0x1 
-                0x080006b8                        _data_addr = LOADADDR (.data)
+                0x0800070c                        . = ALIGN (0x4)
+ *fill*         0x0800070b        0x1 
+                0x0800070c                        _data_addr = LOADADDR (.data)
 
-.glue_7         0x080006b8        0x0
- .glue_7        0x080006b8        0x0 linker stubs
+.glue_7         0x0800070c        0x0
+ .glue_7        0x0800070c        0x0 linker stubs
 
-.glue_7t        0x080006b8        0x0
- .glue_7t       0x080006b8        0x0 linker stubs
+.glue_7t        0x0800070c        0x0
+ .glue_7t       0x0800070c        0x0 linker stubs
 
-.vfp11_veneer   0x080006b8        0x0
- .vfp11_veneer  0x080006b8        0x0 linker stubs
+.vfp11_veneer   0x0800070c        0x0
+ .vfp11_veneer  0x0800070c        0x0 linker stubs
 
-.v4_bx          0x080006b8        0x0
- .v4_bx         0x080006b8        0x0 linker stubs
+.v4_bx          0x0800070c        0x0
+ .v4_bx         0x0800070c        0x0 linker stubs
 
-.iplt           0x080006b8        0x0
- .iplt          0x080006b8        0x0 build/main.o
+.iplt           0x0800070c        0x0
+ .iplt          0x0800070c        0x0 build/main.o
 
-.rel.dyn        0x080006b8        0x0
- .rel.iplt      0x080006b8        0x0 build/main.o
+.rel.dyn        0x0800070c        0x0
+ .rel.iplt      0x0800070c        0x0 build/main.o
 
-.data           0x20000000        0x0 load address 0x080006b8
+.data           0x20000000        0x0 load address 0x0800070c
                 0x20000000                        . = ALIGN (0x4)
                 0x20000000                        _data_start = .
  *(.data)
@@ -302,10 +302,10 @@ LOAD build/usart.o
                 0x20000000                        . = ALIGN (0x4)
                 0x20000000                        _data_end = .
 
-.igot.plt       0x20000000        0x0 load address 0x080006b8
+.igot.plt       0x20000000        0x0 load address 0x0800070c
  .igot.plt      0x20000000        0x0 build/main.o
 
-.bss            0x20000000        0x0 load address 0x080006b8
+.bss            0x20000000        0x0 load address 0x0800070c
                 0x20000000                        . = ALIGN (0x4)
                 0x20000000                        _bss_start = .
  *(.bss)
@@ -315,12 +315,12 @@ LOAD build/usart.o
 OUTPUT(build/final.elf elf32-littlearm)
 LOAD linker stubs
 
-.debug_info     0x00000000      0xf1e
+.debug_info     0x00000000      0xf2b
  .debug_info    0x00000000      0x262 build/gpio.o
  .debug_info    0x00000262      0x47e build/main.o
  .debug_info    0x000006e0      0x188 build/startup.o
  .debug_info    0x00000868      0x335 build/timer.o
- .debug_info    0x00000b9d      0x381 build/usart.o
+ .debug_info    0x00000b9d      0x38e build/usart.o
 
 .debug_abbrev   0x00000000      0x5ae
  .debug_abbrev  0x00000000      0x11d build/gpio.o
@@ -354,7 +354,7 @@ LOAD linker stubs
  .debug_rnglists
                 0x00000073       0x26 build/usart.o
 
-.debug_macro    0x00000000     0x4853
+.debug_macro    0x00000000     0x48cd
  .debug_macro   0x00000000      0xb56 build/gpio.o
  .debug_macro   0x00000b56       0x22 build/gpio.o
  .debug_macro   0x00000b78       0x75 build/gpio.o
@@ -371,37 +371,37 @@ LOAD linker stubs
  .debug_macro   0x000015e1       0x22 build/gpio.o
  .debug_macro   0x00001603       0x46 build/gpio.o
  .debug_macro   0x00001649      0xb89 build/main.o
- .debug_macro   0x000021d2      0x16d build/main.o
- .debug_macro   0x0000233f       0x46 build/main.o
- .debug_macro   0x00002385       0x2e build/main.o
- .debug_macro   0x000023b3       0x22 build/main.o
- .debug_macro   0x000023d5       0x5e build/main.o
- .debug_macro   0x00002433      0xb02 build/startup.o
- .debug_macro   0x00002f35       0x56 build/startup.o
- .debug_macro   0x00002f8b       0x51 build/startup.o
- .debug_macro   0x00002fdc      0xb5c build/timer.o
- .debug_macro   0x00003b38      0x167 build/timer.o
- .debug_macro   0x00003c9f      0xb74 build/usart.o
- .debug_macro   0x00004813       0x40 build/usart.o
+ .debug_macro   0x000021d2      0x19e build/main.o
+ .debug_macro   0x00002370       0x46 build/main.o
+ .debug_macro   0x000023b6       0x2e build/main.o
+ .debug_macro   0x000023e4       0x22 build/main.o
+ .debug_macro   0x00002406       0x76 build/main.o
+ .debug_macro   0x0000247c      0xb02 build/startup.o
+ .debug_macro   0x00002f7e       0x56 build/startup.o
+ .debug_macro   0x00002fd4       0x51 build/startup.o
+ .debug_macro   0x00003025      0xb5c build/timer.o
+ .debug_macro   0x00003b81      0x198 build/timer.o
+ .debug_macro   0x00003d19      0xb74 build/usart.o
+ .debug_macro   0x0000488d       0x40 build/usart.o
 
-.debug_line     0x00000000      0x691
+.debug_line     0x00000000      0x6b6
  .debug_line    0x00000000      0x179 build/gpio.o
- .debug_line    0x00000179      0x1d2 build/main.o
- .debug_line    0x0000034b       0xea build/startup.o
- .debug_line    0x00000435       0xdf build/timer.o
- .debug_line    0x00000514      0x17d build/usart.o
+ .debug_line    0x00000179      0x1da build/main.o
+ .debug_line    0x00000353       0xea build/startup.o
+ .debug_line    0x0000043d       0xdf build/timer.o
+ .debug_line    0x0000051c      0x19a build/usart.o
 
-.debug_str      0x00000000     0x626f
+.debug_str      0x00000000     0x63f5
  .debug_str     0x00000000     0x53d8 build/gpio.o
                                0x5588 (size before relaxing)
- .debug_str     0x000053d8      0xdce build/main.o
-                               0x62e8 (size before relaxing)
- .debug_str     0x000061a6       0x88 build/startup.o
+ .debug_str     0x000053d8      0xf48 build/main.o
+                               0x6462 (size before relaxing)
+ .debug_str     0x00006320       0x88 build/startup.o
                                0x3cdc (size before relaxing)
- .debug_str     0x0000622e        0xc build/timer.o
-                               0x5c41 (size before relaxing)
- .debug_str     0x0000623a       0x35 build/usart.o
-                               0x5fac (size before relaxing)
+ .debug_str     0x000063a8        0xc build/timer.o
+                               0x5d37 (size before relaxing)
+ .debug_str     0x000063b4       0x41 build/usart.o
+                               0x6132 (size before relaxing)
 
 .comment        0x00000000       0x45
  .comment       0x00000000       0x45 build/gpio.o

build/main.i

@@ -2029,6 +2029,11 @@ struct rcc {
 #define RCC_CR_PLLON_ON (1 << RCC_CR_PLLON_BIT)
 
 
+#define RCC_CR_CSS_BIT 19
+#define RCC_CR_CSS_ON (1 << RCC_CR_CSS_BIT)
+
+
+
 #define RCC_CR_HSERDY_BIT 17
 #define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT)
 
@@ -2051,6 +2056,7 @@ struct rcc {
 
 #define RCC_PLLCFGR_PLLSRC_BIT 22
 #define RCC_PLLCFGR_PLLSRC_HSE (1 << RCC_PLLCFGR_PLLSRC_BIT)
+#define RCC_PLLCFGR_PLLSRC_HSI (0 << RCC_PLLCFGR_PLLSRC_BIT)
 
 #define RCC_PLLCFGR_PLLP_BIT 16
 #define RCC_PLLCFGR_PLLP_MASK (0b11)
@@ -2070,12 +2076,14 @@ struct rcc {
 #define RCC_CFGR_PPRE_DIV_2 (0b100)
 
 
+#define RCC_CFGR_MCO1_HSI (0b00)
 #define RCC_CFGR_MCO1_HSE (0b10)
 #define RCC_CFGR_MCO1_PLL (0b11)
 
 #define RCC_CFGR_MCO1_BIT 21
 #define RCC_CFGR_MCO1_MASK (0b11)
 
+#define RCC_CFGR_MCO1PRE_DIV5 (0b111)
 #define RCC_CFGR_MCO1PRE_DIV4 (0b110)
 #define RCC_CFGR_MCO1PRE_DIV2 (0b100)
 
@@ -2110,6 +2118,11 @@ struct rcc {
 #define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT)
 
 
+
+#define RCC_AHB1ENR_GPIOAEN_BIT 0
+#define RCC_AHB1ENR_GPIOAEN_ENABLE (1 << RCC_AHB1ENR_GPIOAEN_BIT)
+
+
 #define RCC_APB1ENR_PWREN_BIT 28
 #define RCC_APB1ENR_PWREN_CLOCK_ENABLE (1 << RCC_APB1ENR_PWREN_BIT)
 
@@ -2287,11 +2300,20 @@ struct usart {
 
 
 
+#define USART_SR_TXE_BIT 7
+#define USART_SR_TXE_TRANSMITTED (1 << USART_SR_TXE_BIT)
+
+
 #define USART_SR_TC_BIT 6
 #define USART_SR_TC_COMPLETED (1 << USART_SR_TC_BIT)
 
 
 
+#define USART_SR_RXNE_BIT 5
+#define USART_SR_RXNE_READY (1 <<USART_SR_RXNE_BIT)
+
+
+
 #define USART_CR1_UE_BIT 13
 #define USART_CR1_UE_ENABLE (1 << USART_CR1_UE_BIT)
 
@@ -2329,11 +2351,13 @@ static void system_clock_init(void) {
 
 
   ((struct rcc *) (0x40023800U))->CR &= ~(1 << 0);
-
-
+# 34 "src/main.c"
   ((struct rcc *) (0x40023800U))->CR |= (1 << 16);
 
 
+  ((struct rcc *) (0x40023800U))->CR |= (1 << 19);
+
+
 
   while (!(((struct rcc *) (0x40023800U))->CR & (1 << 17)));
 
@@ -2397,13 +2421,13 @@ int main(void) {
 
   uint16_t counter = ((struct timer *) (0x40000800U))->CNT;
   
-# 90 "src/main.c" 3 4
+# 102 "src/main.c" 3 4
  _Bool 
-# 90 "src/main.c"
+# 102 "src/main.c"
       led_on = 
-# 90 "src/main.c" 3 4
+# 102 "src/main.c" 3 4
                ((_Bool)+0u)
-# 90 "src/main.c"
+# 102 "src/main.c"
                     ;
   while(1) {
  if ((((struct timer *) (0x40000800U))->CNT - counter) >= 250) {

build/timer.i

@@ -2014,6 +2014,11 @@ struct rcc {
 #define RCC_CR_PLLON_ON (1 << RCC_CR_PLLON_BIT)
 
 
+#define RCC_CR_CSS_BIT 19
+#define RCC_CR_CSS_ON (1 << RCC_CR_CSS_BIT)
+
+
+
 #define RCC_CR_HSERDY_BIT 17
 #define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT)
 
@@ -2036,6 +2041,7 @@ struct rcc {
 
 #define RCC_PLLCFGR_PLLSRC_BIT 22
 #define RCC_PLLCFGR_PLLSRC_HSE (1 << RCC_PLLCFGR_PLLSRC_BIT)
+#define RCC_PLLCFGR_PLLSRC_HSI (0 << RCC_PLLCFGR_PLLSRC_BIT)
 
 #define RCC_PLLCFGR_PLLP_BIT 16
 #define RCC_PLLCFGR_PLLP_MASK (0b11)
@@ -2055,12 +2061,14 @@ struct rcc {
 #define RCC_CFGR_PPRE_DIV_2 (0b100)
 
 
+#define RCC_CFGR_MCO1_HSI (0b00)
 #define RCC_CFGR_MCO1_HSE (0b10)
 #define RCC_CFGR_MCO1_PLL (0b11)
 
 #define RCC_CFGR_MCO1_BIT 21
 #define RCC_CFGR_MCO1_MASK (0b11)
 
+#define RCC_CFGR_MCO1PRE_DIV5 (0b111)
 #define RCC_CFGR_MCO1PRE_DIV4 (0b110)
 #define RCC_CFGR_MCO1PRE_DIV2 (0b100)
 
@@ -2095,6 +2103,11 @@ struct rcc {
 #define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT)
 
 
+
+#define RCC_AHB1ENR_GPIOAEN_BIT 0
+#define RCC_AHB1ENR_GPIOAEN_ENABLE (1 << RCC_AHB1ENR_GPIOAEN_BIT)
+
+
 #define RCC_APB1ENR_PWREN_BIT 28
 #define RCC_APB1ENR_PWREN_CLOCK_ENABLE (1 << RCC_APB1ENR_PWREN_BIT)
 

build/usart.i

@@ -2014,6 +2014,11 @@ struct rcc {
 #define RCC_CR_PLLON_ON (1 << RCC_CR_PLLON_BIT)
 
 
+#define RCC_CR_CSS_BIT 19
+#define RCC_CR_CSS_ON (1 << RCC_CR_CSS_BIT)
+
+
+
 #define RCC_CR_HSERDY_BIT 17
 #define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT)
 
@@ -2036,6 +2041,7 @@ struct rcc {
 
 #define RCC_PLLCFGR_PLLSRC_BIT 22
 #define RCC_PLLCFGR_PLLSRC_HSE (1 << RCC_PLLCFGR_PLLSRC_BIT)
+#define RCC_PLLCFGR_PLLSRC_HSI (0 << RCC_PLLCFGR_PLLSRC_BIT)
 
 #define RCC_PLLCFGR_PLLP_BIT 16
 #define RCC_PLLCFGR_PLLP_MASK (0b11)
@@ -2055,12 +2061,14 @@ struct rcc {
 #define RCC_CFGR_PPRE_DIV_2 (0b100)
 
 
+#define RCC_CFGR_MCO1_HSI (0b00)
 #define RCC_CFGR_MCO1_HSE (0b10)
 #define RCC_CFGR_MCO1_PLL (0b11)
 
 #define RCC_CFGR_MCO1_BIT 21
 #define RCC_CFGR_MCO1_MASK (0b11)
 
+#define RCC_CFGR_MCO1PRE_DIV5 (0b111)
 #define RCC_CFGR_MCO1PRE_DIV4 (0b110)
 #define RCC_CFGR_MCO1PRE_DIV2 (0b100)
 
@@ -2095,6 +2103,11 @@ struct rcc {
 #define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT)
 
 
+
+#define RCC_AHB1ENR_GPIOAEN_BIT 0
+#define RCC_AHB1ENR_GPIOAEN_ENABLE (1 << RCC_AHB1ENR_GPIOAEN_BIT)
+
+
 #define RCC_APB1ENR_PWREN_BIT 28
 #define RCC_APB1ENR_PWREN_CLOCK_ENABLE (1 << RCC_APB1ENR_PWREN_BIT)
 
@@ -2190,11 +2203,20 @@ struct usart {
 
 
 
+#define USART_SR_TXE_BIT 7
+#define USART_SR_TXE_TRANSMITTED (1 << USART_SR_TXE_BIT)
+
+
 #define USART_SR_TC_BIT 6
 #define USART_SR_TC_COMPLETED (1 << USART_SR_TC_BIT)
 
 
 
+#define USART_SR_RXNE_BIT 5
+#define USART_SR_RXNE_READY (1 <<USART_SR_RXNE_BIT)
+
+
+
 #define USART_CR1_UE_BIT 13
 #define USART_CR1_UE_ENABLE (1 << USART_CR1_UE_BIT)
 
@@ -2225,6 +2247,7 @@ void usart2_init(void) {
   ((struct rcc *) (0x40023800U))->AHB1ENR |= (1 << ((('A') - 'A') << 8));
 
 
+
   uint16_t txPin = (((('A') - 'A') << 8) | 2);
   gpio_set_mode(txPin, GPIO_MODE_AF);
   gpio_set_af(txPin, (0b0111));
@@ -2232,14 +2255,26 @@ void usart2_init(void) {
   uint16_t rxPin = (((('A') - 'A') << 8) | 3);
   gpio_set_mode(rxPin, GPIO_MODE_AF);
   gpio_set_af(rxPin, (0b0111));
-# 29 "src/usart.c"
+
+
+  uint16_t clockOutPin = (((('A') - 'A') << 8) | 8);
+  gpio_set_mode(clockOutPin, GPIO_MODE_AF);
+  gpio_set_af(clockOutPin, (0b0000));
+
+  ((struct rcc *) (0x40023800U))->CFGR &= ~((0b11) << 21);
+
+  ((struct rcc *) (0x40023800U))->CFGR |= ((0b11) << 21);
+  ((struct rcc *) (0x40023800U))->CFGR &= ~((0b111) << 24);
+  ((struct rcc *) (0x40023800U))->CFGR |= ((0b110) << 24);
+
+
   ((struct rcc *) (0x40023800U))->APB1ENR |= (1 << 17);
 
 
   ((struct usart *) (0x40004400U))->CR1 = 0;
   ((struct usart *) (0x40004400U))->CR2 = 0;
   ((struct usart *) (0x40004400U))->CR3 = 0;
-# 52 "src/usart.c"
+# 54 "src/usart.c"
   ((struct usart *) (0x40004400U))->BRR &= ~((0b111111111111) << 4);
   ((struct usart *) (0x40004400U))->BRR |= (0x1A << 4);
   ((struct usart *) (0x40004400U))->BRR &= ~((0b111) << 0);
@@ -2255,9 +2290,11 @@ void usart2_start(void) {
 }
 
 void usart2_write_byte(uint8_t c) {
+
   ((struct usart *) (0x40004400U))->DR = c;
 
 
+
   while (!(((struct usart *) (0x40004400U))->SR & (1 << 6)));
 }
 

src/main.c

@@ -24,6 +24,9 @@ static void system_clock_init(void) {
   // Turn on HSE
   RCC->CR |= RCC_CR_HSEON_ON;
 
+  // Turn on clock security system
+  RCC->CR |= RCC_CR_CSS_ON;
+
   // Wait indefinitely for HSE to be ready
   // TODO indicate error/timeout somehow?
   while (!(RCC->CR & RCC_CR_HSERDY_READY));

src/rcc.h

@@ -46,6 +46,11 @@ struct rcc {
 #define RCC_CR_PLLON_BIT 24
 #define RCC_CR_PLLON_ON  (1 << RCC_CR_PLLON_BIT)
 
+// Clock security system
+#define RCC_CR_CSS_BIT 19
+#define RCC_CR_CSS_ON (1 << RCC_CR_CSS_BIT)
+
+
 // HSE clock ready flag
 #define RCC_CR_HSERDY_BIT 17
 #define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT)
@@ -69,6 +74,7 @@ struct rcc {
 
 #define RCC_PLLCFGR_PLLSRC_BIT 22
 #define RCC_PLLCFGR_PLLSRC_HSE (1 << RCC_PLLCFGR_PLLSRC_BIT)
+#define RCC_PLLCFGR_PLLSRC_HSI (0 << RCC_PLLCFGR_PLLSRC_BIT)
 
 #define RCC_PLLCFGR_PLLP_BIT 16 // Bits [17:16]
 #define RCC_PLLCFGR_PLLP_MASK (0b11)
@@ -88,12 +94,14 @@ struct rcc {
 #define RCC_CFGR_PPRE_DIV_2	(0b100)
 
 // Microcontroller clock output 1
+#define RCC_CFGR_MCO1_HSI (0b00)
 #define RCC_CFGR_MCO1_HSE (0b10)
 #define RCC_CFGR_MCO1_PLL (0b11)
 
 #define RCC_CFGR_MCO1_BIT 21 // Bits [22:21]
 #define RCC_CFGR_MCO1_MASK (0b11)
 
+#define RCC_CFGR_MCO1PRE_DIV5 (0b111)
 #define RCC_CFGR_MCO1PRE_DIV4 (0b110)
 #define RCC_CFGR_MCO1PRE_DIV2 (0b100)
 
@@ -127,6 +135,11 @@ struct rcc {
 #define RCC_CFGR_SW_MASK (0b11)
 #define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT)
 
+// AHB1ENR Register
+// GPIOA AHB1ENR
+#define RCC_AHB1ENR_GPIOAEN_BIT 0
+#define RCC_AHB1ENR_GPIOAEN_ENABLE (1 << RCC_AHB1ENR_GPIOAEN_BIT)
+
 // APB1ENR Register
 #define RCC_APB1ENR_PWREN_BIT 28
 #define RCC_APB1ENR_PWREN_CLOCK_ENABLE (1 << RCC_APB1ENR_PWREN_BIT)

src/usart.c

@@ -7,6 +7,7 @@ void usart2_init(void) {
   RCC->AHB1ENR |= (1 << PORT('A'));
 
   // Configure PA2 and PA3 (USART2 pins) to use alternative functions
+  // file:///home/alex/sync/org/stm32-sand/stm32f411ce.pdf#page=48
   uint16_t txPin = PIN('A', 2);
   gpio_set_mode(txPin, GPIO_MODE_AF);
   gpio_set_af(txPin, GPIO_AF_USART2_TX);
@@ -15,15 +16,16 @@ void usart2_init(void) {
   gpio_set_mode(rxPin, GPIO_MODE_AF);
   gpio_set_af(rxPin, GPIO_AF_USART2_RX);
 
-  // Enable MC01; for debugging
-  /* uint16_t clockOutPin = PIN('A', 8); */
-  /* gpio_set_mode(clockOutPin, GPIO_MODE_AF); */
-  /* gpio_set_af(clockOutPin, GPIO_AF_MCO_1); */
-  /* RCC->CFGR &= ~(RCC_CFGR_MCO1_MASK << RCC_CFGR_MCO1_BIT); */
+  // Configure PA8 to output HSE (MCO1)
+  uint16_t clockOutPin = PIN('A', 8);
+  gpio_set_mode(clockOutPin, GPIO_MODE_AF);
+  gpio_set_af(clockOutPin, GPIO_AF_MCO_1);
+
+  RCC->CFGR &= ~(RCC_CFGR_MCO1_MASK << RCC_CFGR_MCO1_BIT);
   /* RCC->CFGR |= (RCC_CFGR_MCO1_HSE << RCC_CFGR_MCO1_BIT); */
-  /* RCC->CFGR |= (RCC_CFGR_MCO1_PLL << RCC_CFGR_MCO1_BIT); */
-  /* RCC->CFGR &= ~(RCC_CFGR_MCO1PRE_MASK << RCC_CFGR_MCO1PRE_BIT); */
-  /* RCC->CFGR |= (RCC_CFGR_MCO1PRE_DIV4 << RCC_CFGR_MCO1PRE_BIT); */
+  RCC->CFGR |= (RCC_CFGR_MCO1_PLL << RCC_CFGR_MCO1_BIT);
+  RCC->CFGR &= ~(RCC_CFGR_MCO1PRE_MASK << RCC_CFGR_MCO1PRE_BIT);
+  RCC->CFGR |= (RCC_CFGR_MCO1PRE_DIV4 << RCC_CFGR_MCO1PRE_BIT);
 
   // Enable USART
   RCC->APB1ENR |= RCC_APB1ENR_USART2EN_ENABLE;
@@ -40,7 +42,7 @@ void usart2_init(void) {
   // USARTDIV = (f_clock / (baud * (8 * (2 - OVER8)))
 
   // Target Baud rate = 115200, f_clock = 48MHz, OVER8 = 0
-  // USARTDIV = 48E6 / (115200 * 8 * 2) = 26.0416666
+  // USARTDIV = (48E6 / (115200 * (8 * 2))) = 26.0416666
   // mantissa = 26 = 0x1A
   // fraction = 0.041666 * 16 = 0.666656 ~= 1
 
@@ -64,9 +66,11 @@ void usart2_start(void) {
 }
 
 void usart2_write_byte(uint8_t c) {
+  // Send data
   USART2->DR = c;
 
   // Wait indefinitely for transmission to be ready for data
+  /* while ((USART2->SR & USART_SR_TXE_TRANSMITTED) == 0); */
   while (!(USART2->SR & USART_SR_TC_COMPLETED));
 }
 

src/usart.h

@@ -10,17 +10,26 @@ struct usart {
   volatile uint32_t CR1;  // Control register 1
   volatile uint32_t CR2;  // Control register 2
   volatile uint32_t CR3;  // Control register 3
-  volatile uint32_t GTPR; // Guard time and prescaler register
+  volatile uint32_t GTPR; // Guard time and prescaler registe
 };
 
 #define USART2_BASE_ADDR (0x40004400U)
 #define USART2 ((struct usart *) USART2_BASE_ADDR)
 
 // SR Register
+// Transmission data register empty
+#define USART_SR_TXE_BIT 7
+#define USART_SR_TXE_TRANSMITTED (1 << USART_SR_TXE_BIT)
+
 // Transmission complete
 #define USART_SR_TC_BIT 6
 #define USART_SR_TC_COMPLETED (1 << USART_SR_TC_BIT)
 
+
+// Read data register not empty
+#define USART_SR_RXNE_BIT 5
+#define USART_SR_RXNE_READY (1 <<USART_SR_RXNE_BIT)
+
 // CR Register
 // USART enable
 #define USART_CR1_UE_BIT 13

todo.txt

@@ -0,0 +1,2 @@
+- implement UART
+- implement tim4 interrupt