alex/stm32-falling-sand
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Add USART support #1

Merged
alex merged 17 commits from uart into main 2025-01-01 12:52:15 +01:00
Conversation 0 Commits 17 Files Changed 28 +3 -3
5 changed files with 3 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Showing only changes of commit a63527a997 - Show all commits

BIN
build/final.elf
View File

Binary file not shown.

2
build/main.S
View File

@@ -150,7 +150,7 @@ system_clock_init:
ldr r3, .L5 ldr r3, .L5
ldr r3, [r3] ldr r3, [r3]
.loc 1 54 47 discriminator 1 .loc 1 54 47 discriminator 1
and r3, r3, #131072 and r3, r3, #33554432
.loc 1 54 10 discriminator 1 .loc 1 54 10 discriminator 1
cmp r3, #0 cmp r3, #0
beq .L3 beq .L3

2
build/main.i
View File

@@ -2288,7 +2288,7 @@ static void system_clock_init(void) {
while (!(((struct rcc *) (0x40023800U))->CR & (1 << 17))); while (!(((struct rcc *) (0x40023800U))->CR & (1 << 25)));
((struct flash *) (0x40023C00U))->ACR |= (1 <<10); ((struct flash *) (0x40023C00U))->ACR |= (1 <<10);

BIN
build/main.o
View File

Binary file not shown.

2
src/main.c
View File

@@ -51,7 +51,7 @@ static void system_clock_init(void) {
// Wait indefinitely for PLL to be ready // Wait indefinitely for PLL to be ready
// TODO indicate error/timeout somehow? // TODO indicate error/timeout somehow?
while (!(RCC->CR & RCC_CR_HSERDY_READY)); while (!(RCC->CR & RCC_CR_PLLRDY_LOCKED));
// Enable caching of instructions and data // Enable caching of instructions and data
FLASH->ACR |= FLASH_ACR_DCEN_ENABLE; FLASH->ACR |= FLASH_ACR_DCEN_ENABLE;