Set correct PLL N for 96MHz
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build/final.elf
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build/final.elf
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@@ -231,7 +231,7 @@ system_clock_init:
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.L5:
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.L5:
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.word 1073887232
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.word 1073887232
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.word 1073770496
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.word 1073770496
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.word 67252505
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.word 67252249
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.word 1073888256
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.word 1073888256
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.cfi_endproc
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.cfi_endproc
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.LFE0:
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.LFE0:
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@@ -2269,7 +2269,7 @@ static void system_clock_init(void) {
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((struct rcc *) (0x40023800U))->PLLCFGR |= (1 << 22);
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((struct rcc *) (0x40023800U))->PLLCFGR |= (1 << 22);
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((struct rcc *) (0x40023800U))->PLLCFGR |= ((25 & (0b111111)) << 0) | ((196 & (0b111111111)) << 6) | ((2 & (0b11)) << 16) | ((4 & (0b1111)) << 24);
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((struct rcc *) (0x40023800U))->PLLCFGR |= ((25 & (0b111111)) << 0) | ((192 & (0b111111111)) << 6) | ((2 & (0b11)) << 16) | ((4 & (0b1111)) << 24);
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((struct rcc *) (0x40023800U))->CFGR &= ~((0b1111) << 4);
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((struct rcc *) (0x40023800U))->CFGR &= ~((0b1111) << 4);
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BIN
build/main.o
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build/main.o
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@@ -32,7 +32,7 @@ static void system_clock_init(void) {
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RCC->PLLCFGR |= RCC_PLLCFGR_PLLSRC_HSE;
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RCC->PLLCFGR |= RCC_PLLCFGR_PLLSRC_HSE;
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// Settings to achieve system clock of 96Mhz
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// Settings to achieve system clock of 96Mhz
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RCC->PLLCFGR |= RCC_PLLCFGR_PLLM(25) | RCC_PLLCFGR_PLLN(196) | RCC_PLLCFGR_PLLP(2) | RCC_PLLCFGR_PLLQ(4);
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RCC->PLLCFGR |= RCC_PLLCFGR_PLLM(25) | RCC_PLLCFGR_PLLN(192) | RCC_PLLCFGR_PLLP(2) | RCC_PLLCFGR_PLLQ(4);
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// Set AHB prescalar to /1
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// Set AHB prescalar to /1
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RCC->CFGR &= ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_BIT);
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RCC->CFGR &= ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_BIT);
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