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base: alex/stm32-falling-sand:1a1bfda5cf03367d92b0f1e224572a648ceb5a46
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alex/stm32-falling-sand:main alex/stm32-falling-sand:uart
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compare: alex/stm32-falling-sand:uart
Branches Tags
alex/stm32-falling-sand:main alex/stm32-falling-sand:uart

17 Commits
1a1bfda5cf .. uart

Author SHA1 Message Date
Alexander Heldt 68f6d98f1f Add README 2025-01-01 12:50:22 +01:00
Alexander Heldt 4600e8e838 Disable FLASH wait states 
As it blocks the mc from reaching a ready state for unknown reason(s)
 2025-01-01 12:50:22 +01:00
Alexander Heldt 1ae81edf57 Add ability to debug clock with MCO1 2025-01-01 12:49:31 +01:00
Alexander Heldt 55ee09eab8 Use USART2 2025-01-01 12:49:18 +01:00
Alexander Heldt 95455a7161 Add usart.{h, c} 2025-01-01 12:49:04 +01:00
Alexander Heldt 992b3c5b97 Add gpio_set_af to set alternative function of a pin 2025-01-01 12:47:01 +01:00
Alexander Heldt 3f95f00852 Add PORT macro 
And use it in the `PIN` macro
 2025-01-01 12:46:44 +01:00
Alexander Heldt 2a1e3a41da Fix gpio_set_mode masking 2025-01-01 12:46:31 +01:00
Alexander Heldt 152a9ad8a7 Remove BIT macro 2025-01-01 12:46:01 +01:00
Alexander Heldt 980b9a2d9b GPIO alternative function registers are 32bit each, not 64bit 2025-01-01 12:44:28 +01:00
Alexander Heldt 3aad7271a1 Use RCC_CFGR_SW helper function to set software clock 2025-01-01 12:44:10 +01:00
Alexander Heldt 11f469564f Turn off HSI earlier 2025-01-01 12:43:48 +01:00
Alexander Heldt 916d7d9620 Set correct PLL N for 96MHz 2025-01-01 12:43:43 +01:00
Alexander Heldt a63527a997 Correctly check PLL readiness 2025-01-01 12:43:19 +01:00
Alexander Heldt a1c43ad21c TIM4 runs at 96MHz, not 48MHz 2025-01-01 12:42:46 +01:00
Alexander Heldt 8f3285072b Generalise naming of TIMx_ENABLE 2025-01-01 12:42:26 +01:00
Alexander Heldt 908cfda5b3 Add stm32cubemx in dev shell 2024-12-30 11:39:53 +01:00
23 changed files with 2298 additions and 2665 deletions
Expand all files Collapse all files
build/final.elf
BIN
View File
Binary file not shown.
build/final.elf.map
+179 -176
View File
@@ -53,7 +53,7 @@ Discarded input sections
.debug_macro 0x00000000 0x89 build/main.o .debug_macro 0x00000000 0x89 build/main.o
.debug_macro 0x00000000 0x4cc build/main.o .debug_macro 0x00000000 0x4cc build/main.o
.debug_macro 0x00000000 0x22 build/main.o .debug_macro 0x00000000 0x22 build/main.o
.debug_macro 0x00000000 0xa0 build/main.o .debug_macro 0x00000000 0x46 build/main.o
.group 0x00000000 0xc build/startup.o .group 0x00000000 0xc build/startup.o
.group 0x00000000 0xc build/startup.o .group 0x00000000 0xc build/startup.o
.group 0x00000000 0xc build/startup.o .group 0x00000000 0xc build/startup.o
@@ -128,9 +128,9 @@ Discarded input sections
.debug_macro 0x00000000 0x1df build/usart.o .debug_macro 0x00000000 0x1df build/usart.o
.debug_macro 0x00000000 0x89 build/usart.o .debug_macro 0x00000000 0x89 build/usart.o
.debug_macro 0x00000000 0x4cc build/usart.o .debug_macro 0x00000000 0x4cc build/usart.o
.debug_macro 0x00000000 0x19f build/usart.o .debug_macro 0x00000000 0x167 build/usart.o
.debug_macro 0x00000000 0x22 build/usart.o .debug_macro 0x00000000 0x22 build/usart.o
.debug_macro 0x00000000 0x82 build/usart.o .debug_macro 0x00000000 0x5e build/usart.o
Memory Configuration Memory Configuration
@@ -157,141 +157,144 @@ LOAD build/usart.o
0x08000000 interrupt_vector_table 0x08000000 interrupt_vector_table
0x08000198 . = ALIGN (0x4) 0x08000198 . = ALIGN (0x4)
.text 0x08000198 0x4d4 .text 0x08000198 0x520
0x08000198 . = ALIGN (0x4) 0x08000198 . = ALIGN (0x4)
*(.text) *(.text)
*(.text.*) *(.text.*)
.text.gpio_set_mode .text.gpio_set_mode
0x08000198 0x62 build/gpio.o 0x08000198 0x62 build/gpio.o
0x08000198 gpio_set_mode 0x08000198 gpio_set_mode
.text.gpio_set_af
0x080001fa 0x98 build/gpio.o
0x080001fa gpio_set_af
.text.gpio_write .text.gpio_write
0x080001fa 0x4c build/gpio.o 0x08000292 0x4c build/gpio.o
0x080001fa gpio_write 0x08000292 gpio_write
*fill* 0x08000246 0x2 *fill* 0x080002de 0x2
.text.system_clock_init .text.system_clock_init
0x08000248 0x128 build/main.o 0x080002e0 0x11c build/main.o
.text.main 0x08000370 0x9c build/main.o .text.main 0x080003fc 0x9c build/main.o
0x08000370 main 0x080003fc main
.text.init_memory .text.init_memory
0x0800040c 0x64 build/startup.o 0x08000498 0x64 build/startup.o
0x0800040c init_memory 0x08000498 init_memory
.text.reset 0x08000470 0x10 build/startup.o .text.reset 0x080004fc 0x10 build/startup.o
0x08000470 reset 0x080004fc reset
.text.default_handler .text.default_handler
0x08000480 0x8 build/startup.o 0x0800050c 0x8 build/startup.o
0x08000480 exti0 0x0800050c exti0
0x08000480 debug_monitor 0x0800050c debug_monitor
0x08000480 rcc 0x0800050c rcc
0x08000480 x 0x0800050c x
0x08000480 sdio 0x0800050c sdio
0x08000480 usage_fault 0x0800050c usage_fault
0x08000480 tim1_up_tim10 0x0800050c tim1_up_tim10
0x08000480 usart1 0x0800050c usart1
0x08000480 i2c3_er 0x0800050c i2c3_er
0x08000480 spi2 0x0800050c spi2
0x08000480 dma1_stream1 0x0800050c dma1_stream1
0x08000480 bus_fault 0x0800050c bus_fault
0x08000480 spi5 0x0800050c spi5
0x08000480 exti3 0x0800050c exti3
0x08000480 dma2_stream5 0x0800050c dma2_stream5
0x08000480 tim2 0x0800050c tim2
0x08000480 dma1_stream6 0x0800050c dma1_stream6
0x08000480 default_handler 0x0800050c default_handler
0x08000480 i2c1_er 0x0800050c i2c1_er
0x08000480 hard_fault 0x0800050c hard_fault
0x08000480 usart6 0x0800050c usart6
0x08000480 exti15_10 0x0800050c exti15_10
0x08000480 usart2 0x0800050c usart2
0x08000480 pend_sv 0x0800050c pend_sv
0x08000480 i2c1_ev 0x0800050c i2c1_ev
0x08000480 wwdg 0x0800050c wwdg
0x08000480 adc 0x0800050c adc
0x08000480 rtc_alarm 0x0800050c rtc_alarm
0x08000480 spi3 0x0800050c spi3
0x08000480 exti1 0x0800050c exti1
0x08000480 mem_manage 0x0800050c mem_manage
0x08000480 dma2_stream1 0x0800050c dma2_stream1
0x08000480 dma1_stream2 0x0800050c dma1_stream2
0x08000480 dma2_stream3 0x0800050c dma2_stream3
0x08000480 sv_call 0x0800050c sv_call
0x08000480 tim3 0x0800050c tim3
0x08000480 otg_fs 0x0800050c otg_fs
0x08000480 dma1_stream5 0x0800050c dma1_stream5
0x08000480 dma2_stream6 0x0800050c dma2_stream6
0x08000480 flash 0x0800050c flash
0x08000480 tamp_stamp 0x0800050c tamp_stamp
0x08000480 i2c3_ev 0x0800050c i2c3_ev
0x08000480 rtc_wkup 0x0800050c rtc_wkup
0x08000480 dma2_stream0 0x0800050c dma2_stream0
0x08000480 pvd 0x0800050c pvd
0x08000480 fpu 0x0800050c fpu
0x08000480 exti4 0x0800050c exti4
0x08000480 exti2 0x0800050c exti2
0x08000480 spi1 0x0800050c spi1
0x08000480 dma1_stream0 0x0800050c dma1_stream0
0x08000480 tim1_brk_tim9 0x0800050c tim1_brk_tim9
0x08000480 i2c2_ev 0x0800050c i2c2_ev
0x08000480 otg_fs_wkup 0x0800050c otg_fs_wkup
0x08000480 spi4 0x0800050c spi4
0x08000480 dma2_stream2 0x0800050c dma2_stream2
0x08000480 tim1_cc 0x0800050c tim1_cc
0x08000480 tim1_trg_com_tim11 0x0800050c tim1_trg_com_tim11
0x08000480 exti9_5 0x0800050c exti9_5
0x08000480 dma1_stream3 0x0800050c dma1_stream3
0x08000480 dma2_stream4 0x0800050c dma2_stream4
0x08000480 i2c2_er 0x0800050c i2c2_er
0x08000480 dma2_stream7 0x0800050c dma2_stream7
0x08000480 dma1_stream7 0x0800050c dma1_stream7
0x08000480 nmi 0x0800050c nmi
0x08000480 systick 0x0800050c systick
0x08000480 tim4 0x0800050c tim4
0x08000480 tim5 0x0800050c tim5
0x08000480 dma1_stream4 0x0800050c dma1_stream4
.text.tim4_init .text.tim4_init
0x08000488 0x40 build/timer.o 0x08000514 0x40 build/timer.o
0x08000488 tim4_init 0x08000514 tim4_init
.text.tim4_start .text.tim4_start
0x080004c8 0x20 build/timer.o 0x08000554 0x20 build/timer.o
0x080004c8 tim4_start 0x08000554 tim4_start
.text.usart2_init .text.usart2_init
0x080004e8 0xf8 build/usart.o 0x08000574 0xb8 build/usart.o
0x080004e8 usart2_init 0x08000574 usart2_init
.text.usart2_start .text.usart2_start
0x080005e0 0x20 build/usart.o 0x0800062c 0x20 build/usart.o
0x080005e0 usart2_start 0x0800062c usart2_start
.text.usart2_write_byte .text.usart2_write_byte
0x08000600 0x30 build/usart.o 0x0800064c 0x30 build/usart.o
0x08000600 usart2_write_byte 0x0800064c usart2_write_byte
.text.usart2_write .text.usart2_write
0x08000630 0x2a build/usart.o 0x0800067c 0x2a build/usart.o
0x08000630 usart2_write 0x0800067c usart2_write
*(.rodata) *(.rodata)
*fill* 0x0800065a 0x2 *fill* 0x080006a6 0x2
.rodata 0x0800065c 0xf build/main.o .rodata 0x080006a8 0xf build/main.o
*(.rodata.*) *(.rodata.*)
0x0800066c . = ALIGN (0x4) 0x080006b8 . = ALIGN (0x4)
*fill* 0x0800066b 0x1 *fill* 0x080006b7 0x1
0x0800066c _data_addr = LOADADDR (.data) 0x080006b8 _data_addr = LOADADDR (.data)
.glue_7 0x0800066c 0x0 .glue_7 0x080006b8 0x0
.glue_7 0x0800066c 0x0 linker stubs .glue_7 0x080006b8 0x0 linker stubs
.glue_7t 0x0800066c 0x0 .glue_7t 0x080006b8 0x0
.glue_7t 0x0800066c 0x0 linker stubs .glue_7t 0x080006b8 0x0 linker stubs
.vfp11_veneer 0x0800066c 0x0 .vfp11_veneer 0x080006b8 0x0
.vfp11_veneer 0x0800066c 0x0 linker stubs .vfp11_veneer 0x080006b8 0x0 linker stubs
.v4_bx 0x0800066c 0x0 .v4_bx 0x080006b8 0x0
.v4_bx 0x0800066c 0x0 linker stubs .v4_bx 0x080006b8 0x0 linker stubs
.iplt 0x0800066c 0x0 .iplt 0x080006b8 0x0
.iplt 0x0800066c 0x0 build/main.o .iplt 0x080006b8 0x0 build/main.o
.rel.dyn 0x0800066c 0x0 .rel.dyn 0x080006b8 0x0
.rel.iplt 0x0800066c 0x0 build/main.o .rel.iplt 0x080006b8 0x0 build/main.o
.data 0x20000000 0x0 load address 0x0800066c .data 0x20000000 0x0 load address 0x080006b8
0x20000000 . = ALIGN (0x4) 0x20000000 . = ALIGN (0x4)
0x20000000 _data_start = . 0x20000000 _data_start = .
*(.data) *(.data)
@@ -299,10 +302,10 @@ LOAD build/usart.o
0x20000000 . = ALIGN (0x4) 0x20000000 . = ALIGN (0x4)
0x20000000 _data_end = . 0x20000000 _data_end = .
.igot.plt 0x20000000 0x0 load address 0x0800066c .igot.plt 0x20000000 0x0 load address 0x080006b8
.igot.plt 0x20000000 0x0 build/main.o .igot.plt 0x20000000 0x0 build/main.o
.bss 0x20000000 0x0 load address 0x0800066c .bss 0x20000000 0x0 load address 0x080006b8
0x20000000 . = ALIGN (0x4) 0x20000000 . = ALIGN (0x4)
0x20000000 _bss_start = . 0x20000000 _bss_start = .
*(.bss) *(.bss)
@@ -312,46 +315,46 @@ LOAD build/usart.o
OUTPUT(build/final.elf elf32-littlearm) OUTPUT(build/final.elf elf32-littlearm)
LOAD linker stubs LOAD linker stubs
.debug_info 0x00000000 0xeb1 .debug_info 0x00000000 0xf1e
.debug_info 0x00000000 0x205 build/gpio.o .debug_info 0x00000000 0x262 build/gpio.o
.debug_info 0x00000205 0x47e build/main.o .debug_info 0x00000262 0x47e build/main.o
.debug_info 0x00000683 0x188 build/startup.o .debug_info 0x000006e0 0x188 build/startup.o
.debug_info 0x0000080b 0x335 build/timer.o .debug_info 0x00000868 0x335 build/timer.o
.debug_info 0x00000b40 0x371 build/usart.o .debug_info 0x00000b9d 0x381 build/usart.o
.debug_abbrev 0x00000000 0x547 .debug_abbrev 0x00000000 0x5ae
.debug_abbrev 0x00000000 0x119 build/gpio.o .debug_abbrev 0x00000000 0x11d build/gpio.o
.debug_abbrev 0x00000119 0x14b build/main.o .debug_abbrev 0x0000011d 0x14b build/main.o
.debug_abbrev 0x00000264 0x127 build/startup.o .debug_abbrev 0x00000268 0x127 build/startup.o
.debug_abbrev 0x0000038b 0xb5 build/timer.o .debug_abbrev 0x0000038f 0xb5 build/timer.o
.debug_abbrev 0x00000440 0x107 build/usart.o .debug_abbrev 0x00000444 0x16a build/usart.o
.debug_aranges 0x00000000 0xe0 .debug_aranges 0x00000000 0xe8
.debug_aranges .debug_aranges
0x00000000 0x28 build/gpio.o 0x00000000 0x30 build/gpio.o
.debug_aranges .debug_aranges
0x00000028 0x28 build/main.o 0x00000030 0x28 build/main.o
.debug_aranges .debug_aranges
0x00000050 0x30 build/startup.o 0x00000058 0x30 build/startup.o
.debug_aranges .debug_aranges
0x00000080 0x28 build/timer.o 0x00000088 0x28 build/timer.o
.debug_aranges .debug_aranges
0x000000a8 0x38 build/usart.o 0x000000b0 0x38 build/usart.o
.debug_rnglists .debug_rnglists
0x00000000 0x92 0x00000000 0x99
.debug_rnglists .debug_rnglists
0x00000000 0x19 build/gpio.o 0x00000000 0x20 build/gpio.o
.debug_rnglists .debug_rnglists
0x00000019 0x1b build/main.o 0x00000020 0x1b build/main.o
.debug_rnglists .debug_rnglists
0x00000034 0x1f build/startup.o 0x0000003b 0x1f build/startup.o
.debug_rnglists .debug_rnglists
0x00000053 0x19 build/timer.o 0x0000005a 0x19 build/timer.o
.debug_rnglists .debug_rnglists
0x0000006c 0x26 build/usart.o 0x00000073 0x26 build/usart.o
.debug_macro 0x00000000 0x499b .debug_macro 0x00000000 0x4853
.debug_macro 0x00000000 0xb56 build/gpio.o .debug_macro 0x00000000 0xb56 build/gpio.o
.debug_macro 0x00000b56 0x22 build/gpio.o .debug_macro 0x00000b56 0x22 build/gpio.o
.debug_macro 0x00000b78 0x75 build/gpio.o .debug_macro 0x00000b78 0x75 build/gpio.o
@@ -366,39 +369,39 @@ LOAD linker stubs
.debug_macro 0x0000108c 0x89 build/gpio.o .debug_macro 0x0000108c 0x89 build/gpio.o
.debug_macro 0x00001115 0x4cc build/gpio.o .debug_macro 0x00001115 0x4cc build/gpio.o
.debug_macro 0x000015e1 0x22 build/gpio.o .debug_macro 0x000015e1 0x22 build/gpio.o
.debug_macro 0x00001603 0xa0 build/gpio.o .debug_macro 0x00001603 0x46 build/gpio.o
.debug_macro 0x000016a3 0xb89 build/main.o .debug_macro 0x00001649 0xb89 build/main.o
.debug_macro 0x0000222c 0x1a5 build/main.o .debug_macro 0x000021d2 0x16d build/main.o
.debug_macro 0x000023d1 0x46 build/main.o .debug_macro 0x0000233f 0x46 build/main.o
.debug_macro 0x00002417 0x2e build/main.o .debug_macro 0x00002385 0x2e build/main.o
.debug_macro 0x00002445 0x22 build/main.o .debug_macro 0x000023b3 0x22 build/main.o
.debug_macro 0x00002467 0x82 build/main.o .debug_macro 0x000023d5 0x5e build/main.o
.debug_macro 0x000024e9 0xb02 build/startup.o .debug_macro 0x00002433 0xb02 build/startup.o
.debug_macro 0x00002feb 0x56 build/startup.o .debug_macro 0x00002f35 0x56 build/startup.o
.debug_macro 0x00003041 0x51 build/startup.o .debug_macro 0x00002f8b 0x51 build/startup.o
.debug_macro 0x00003092 0xb5c build/timer.o .debug_macro 0x00002fdc 0xb5c build/timer.o
.debug_macro 0x00003bee 0x19f build/timer.o .debug_macro 0x00003b38 0x167 build/timer.o
.debug_macro 0x00003d8d 0xb74 build/usart.o .debug_macro 0x00003c9f 0xb74 build/usart.o
.debug_macro 0x00004901 0x9a build/usart.o .debug_macro 0x00004813 0x40 build/usart.o
.debug_line 0x00000000 0x65d .debug_line 0x00000000 0x691
.debug_line 0x00000000 0x116 build/gpio.o .debug_line 0x00000000 0x179 build/gpio.o
.debug_line 0x00000116 0x1da build/main.o .debug_line 0x00000179 0x1d2 build/main.o
.debug_line 0x000002f0 0xea build/startup.o .debug_line 0x0000034b 0xea build/startup.o
.debug_line 0x000003da 0xdf build/timer.o .debug_line 0x00000435 0xdf build/timer.o
.debug_line 0x000004b9 0x1a4 build/usart.o .debug_line 0x00000514 0x17d build/usart.o
.debug_str 0x00000000 0x65c7 .debug_str 0x00000000 0x626f
.debug_str 0x00000000 0x5574 build/gpio.o .debug_str 0x00000000 0x53d8 build/gpio.o
0x571c (size before relaxing) 0x5588 (size before relaxing)
.debug_str 0x00005574 0xf8c build/main.o .debug_str 0x000053d8 0xdce build/main.o
0x6658 (size before relaxing) 0x62e8 (size before relaxing)
.debug_str 0x00006500 0x88 build/startup.o .debug_str 0x000061a6 0x88 build/startup.o
0x3cdc (size before relaxing) 0x3cdc (size before relaxing)
.debug_str 0x00006588 0xc build/timer.o .debug_str 0x0000622e 0xc build/timer.o
0x5d37 (size before relaxing) 0x5c41 (size before relaxing)
.debug_str 0x00006594 0x33 build/usart.o .debug_str 0x0000623a 0x35 build/usart.o
0x62cd (size before relaxing) 0x5fac (size before relaxing)
.comment 0x00000000 0x45 .comment 0x00000000 0x45
.comment 0x00000000 0x45 build/gpio.o .comment 0x00000000 0x45 build/gpio.o
@@ -439,9 +442,9 @@ LOAD linker stubs
0x00000288 0x8 build/usart.o 0x00000288 0x8 build/usart.o
0x26c (size before relaxing) 0x26c (size before relaxing)
.debug_frame 0x00000000 0x208 .debug_frame 0x00000000 0x234
.debug_frame 0x00000000 0x60 build/gpio.o .debug_frame 0x00000000 0x88 build/gpio.o
.debug_frame 0x00000060 0x50 build/main.o .debug_frame 0x00000088 0x50 build/main.o
.debug_frame 0x000000b0 0x6c build/startup.o .debug_frame 0x000000d8 0x6c build/startup.o
.debug_frame 0x0000011c 0x50 build/timer.o .debug_frame 0x00000144 0x50 build/timer.o
.debug_frame 0x0000016c 0x9c build/usart.o .debug_frame 0x00000194 0xa0 build/usart.o
build/gpio.S
+534 -424
View File
File diff suppressed because it is too large Load Diff
build/gpio.i
+25 -38
View File
@@ -1999,45 +1999,19 @@ struct gpio {
volatile uint32_t AFRH; volatile uint32_t AFRH;
}; };
#define GPIOA_BASE_ADDR (0x40020000U)
#define GPIOA ((struct gpio *) GPIOA_BASE_ADDR)
#define GPIO_MODER_AF_MODE (0b10)
#define GPIO_MODER_MODER8_BIT 16
#define GPIO_MODER_MODER8_MASK (0b11)
#define GPIO_MODER_MODER3_BIT 6
#define GPIO_MODER_MODER3_MASK (0b11)
#define GPIO_MODER_MODER2_BIT 4
#define GPIO_MODER_MODER2_MASK (0b11)
#define GPIO_AFRH_AFRH8_BIT 0
#define GPIO_AFRH_AFRH8_MASK (0b1111)
#define GPIO_AFRH_AFRH8_MCO_1 (0b0000)
#define GPIO_AFRL_AFRL3_BIT 12
#define GPIO_AFRL_AFRL3_MASK (0b1111)
#define GPIO_AFRL_AFRL3_USART2_RX (0b0111)
#define GPIO_AFRL_AFRL2_BIT 8
#define GPIO_AFRL_AFRL2_MASK (0b1111)
#define GPIO_AFRL_AFRL2_USART2_TX (0b0111)
#define GPIO_AF_MCO_1 (0b0000)
#define GPIO_AF_USART2_RX (0b0111)
#define GPIO_AF_USART2_TX (0b0111)
#define GPIO_BASE_ADDR (0x40020000U) #define GPIO_BASE_ADDR (0x40020000U)
#define GPIO_PORT_OFFSET (0x400U) #define GPIO_PORT_OFFSET (0x400U)
#define GPIO(port) ((struct gpio*)(uintptr_t)(GPIO_BASE_ADDR + (GPIO_PORT_OFFSET * port))) #define GPIO(port) ((struct gpio*)(uintptr_t)(GPIO_BASE_ADDR + (GPIO_PORT_OFFSET * port)))
#define BIT(x) (1 << x)
#define PIN(port,num) ((((port) - 'A') << 8) | num) #define PORT(port) (((port) - 'A') << 8)
#define PIN(port,num) (PORT(port) | num)
#define PINNUM(pin) (pin & 0b1111) #define PINNUM(pin) (pin & 0b1111)
@@ -2051,24 +2025,37 @@ typedef enum {
} GPIO_MODE; } GPIO_MODE;
void gpio_set_mode(uint16_t pin, GPIO_MODE mode); void gpio_set_mode(uint16_t pin, GPIO_MODE mode);
void gpio_set_af(uint16_t pin, uint8_t af);
void gpio_write(uint16_t pin, void gpio_write(uint16_t pin,
# 72 "src/gpio.h" 3 4 # 47 "src/gpio.h" 3 4
_Bool _Bool
# 72 "src/gpio.h" # 47 "src/gpio.h"
val); val);
# 5 "src/gpio.c" 2 # 5 "src/gpio.c" 2
void gpio_set_mode(uint16_t pin, GPIO_MODE mode) { void gpio_set_mode(uint16_t pin, GPIO_MODE mode) {
struct gpio *gpio = ((struct gpio*)(uintptr_t)((0x40020000U) + ((0x400U) * (pin >> 8)))); struct gpio *gpio = ((struct gpio*)(uintptr_t)((0x40020000U) + ((0x400U) * (pin >> 8))));
int pn = (pin & 0b1111); int pn = (pin & 0b1111);
gpio->MODER &= ~(0x0011 << (pn * 2)); gpio->MODER &= ~(0b11 << (pn * 2));
gpio->MODER |= (mode & 0b011) << (pn * 2); gpio->MODER |= (mode & 0b11) << (pn * 2);
}
void gpio_set_af(uint16_t pin, uint8_t af) {
struct gpio *gpio = ((struct gpio*)(uintptr_t)((0x40020000U) + ((0x400U) * (pin >> 8))));
int pn = (pin & 0b1111);
if (pn < 8) {
gpio->AFRL &= ~(0b1111 << (pn * 4));
gpio->AFRL |= (af & 0b1111) << (pn * 4);
} else {
gpio->AFRH &= ~(0b1111 << (pn * 4));
gpio->AFRH |= (af & 0b1111) << (pn * 4);
}
} }
void gpio_write(uint16_t pin, void gpio_write(uint16_t pin,
# 13 "src/gpio.c" 3 4 # 25 "src/gpio.c" 3 4
_Bool _Bool
# 13 "src/gpio.c" # 25 "src/gpio.c"
val) { val) {
struct gpio *gpio = ((struct gpio*)(uintptr_t)((0x40020000U) + ((0x400U) * (pin >> 8)))); struct gpio *gpio = ((struct gpio*)(uintptr_t)((0x40020000U) + ((0x400U) * (pin >> 8))));
gpio->BSRR = (0b0011 << (pin & 0b1111)) << (val ? 0 : 16); gpio->BSRR = (0b0011 << (pin & 0b1111)) << (val ? 0 : 16);
build/gpio.o
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build/main.S
+497 -649
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build/main.i
+16 -71
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@@ -2029,11 +2029,6 @@ struct rcc {
#define RCC_CR_PLLON_ON (1 << RCC_CR_PLLON_BIT) #define RCC_CR_PLLON_ON (1 << RCC_CR_PLLON_BIT)
#define RCC_CR_CSS_BIT 19
#define RCC_CR_CSS_ON (1 << RCC_CR_CSS_BIT)
#define RCC_CR_HSERDY_BIT 17 #define RCC_CR_HSERDY_BIT 17
#define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT) #define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT)
@@ -2056,7 +2051,6 @@ struct rcc {
#define RCC_PLLCFGR_PLLSRC_BIT 22 #define RCC_PLLCFGR_PLLSRC_BIT 22
#define RCC_PLLCFGR_PLLSRC_HSE (1 << RCC_PLLCFGR_PLLSRC_BIT) #define RCC_PLLCFGR_PLLSRC_HSE (1 << RCC_PLLCFGR_PLLSRC_BIT)
#define RCC_PLLCFGR_PLLSRC_HSI (0 << RCC_PLLCFGR_PLLSRC_BIT)
#define RCC_PLLCFGR_PLLP_BIT 16 #define RCC_PLLCFGR_PLLP_BIT 16
#define RCC_PLLCFGR_PLLP_MASK (0b11) #define RCC_PLLCFGR_PLLP_MASK (0b11)
@@ -2076,14 +2070,12 @@ struct rcc {
#define RCC_CFGR_PPRE_DIV_2 (0b100) #define RCC_CFGR_PPRE_DIV_2 (0b100)
#define RCC_CFGR_MCO1_HSI (0b00)
#define RCC_CFGR_MCO1_HSE (0b10) #define RCC_CFGR_MCO1_HSE (0b10)
#define RCC_CFGR_MCO1_PLL (0b11) #define RCC_CFGR_MCO1_PLL (0b11)
#define RCC_CFGR_MCO1_BIT 21 #define RCC_CFGR_MCO1_BIT 21
#define RCC_CFGR_MCO1_MASK (0b11) #define RCC_CFGR_MCO1_MASK (0b11)
#define RCC_CFGR_MCO1PRE_DIV5 (0b111)
#define RCC_CFGR_MCO1PRE_DIV4 (0b110) #define RCC_CFGR_MCO1PRE_DIV4 (0b110)
#define RCC_CFGR_MCO1PRE_DIV2 (0b100) #define RCC_CFGR_MCO1PRE_DIV2 (0b100)
@@ -2111,7 +2103,6 @@ struct rcc {
#define RCC_CFGR_SWS_MASK (0b11) #define RCC_CFGR_SWS_MASK (0b11)
#define RCC_CFGR_SW_PLL (0b10)
#define RCC_CFGR_SW_PLL (0b10) #define RCC_CFGR_SW_PLL (0b10)
#define RCC_CFGR_SW_BIT 0 #define RCC_CFGR_SW_BIT 0
@@ -2119,11 +2110,6 @@ struct rcc {
#define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT) #define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT)
#define RCC_AHB1ENR_GPIOAEN_BIT 0
#define RCC_AHB1ENR_GPIOAEN_ENABLE (1 << RCC_AHB1ENR_GPIOAEN_BIT)
#define RCC_APB1ENR_PWREN_BIT 28 #define RCC_APB1ENR_PWREN_BIT 28
#define RCC_APB1ENR_PWREN_CLOCK_ENABLE (1 << RCC_APB1ENR_PWREN_BIT) #define RCC_APB1ENR_PWREN_CLOCK_ENABLE (1 << RCC_APB1ENR_PWREN_BIT)
@@ -2153,45 +2139,19 @@ struct gpio {
volatile uint32_t AFRH; volatile uint32_t AFRH;
}; };
#define GPIOA_BASE_ADDR (0x40020000U)
#define GPIOA ((struct gpio *) GPIOA_BASE_ADDR)
#define GPIO_MODER_AF_MODE (0b10)
#define GPIO_MODER_MODER8_BIT 16
#define GPIO_MODER_MODER8_MASK (0b11)
#define GPIO_MODER_MODER3_BIT 6
#define GPIO_MODER_MODER3_MASK (0b11)
#define GPIO_MODER_MODER2_BIT 4
#define GPIO_MODER_MODER2_MASK (0b11)
#define GPIO_AFRH_AFRH8_BIT 0
#define GPIO_AFRH_AFRH8_MASK (0b1111)
#define GPIO_AFRH_AFRH8_MCO_1 (0b0000)
#define GPIO_AFRL_AFRL3_BIT 12
#define GPIO_AFRL_AFRL3_MASK (0b1111)
#define GPIO_AFRL_AFRL3_USART2_RX (0b0111)
#define GPIO_AFRL_AFRL2_BIT 8
#define GPIO_AFRL_AFRL2_MASK (0b1111)
#define GPIO_AFRL_AFRL2_USART2_TX (0b0111)
#define GPIO_AF_MCO_1 (0b0000)
#define GPIO_AF_USART2_RX (0b0111)
#define GPIO_AF_USART2_TX (0b0111)
#define GPIO_BASE_ADDR (0x40020000U) #define GPIO_BASE_ADDR (0x40020000U)
#define GPIO_PORT_OFFSET (0x400U) #define GPIO_PORT_OFFSET (0x400U)
#define GPIO(port) ((struct gpio*)(uintptr_t)(GPIO_BASE_ADDR + (GPIO_PORT_OFFSET * port))) #define GPIO(port) ((struct gpio*)(uintptr_t)(GPIO_BASE_ADDR + (GPIO_PORT_OFFSET * port)))
#define BIT(x) (1 << x)
#define PIN(port,num) ((((port) - 'A') << 8) | num) #define PORT(port) (((port) - 'A') << 8)
#define PIN(port,num) (PORT(port) | num)
#define PINNUM(pin) (pin & 0b1111) #define PINNUM(pin) (pin & 0b1111)
@@ -2205,10 +2165,11 @@ typedef enum {
} GPIO_MODE; } GPIO_MODE;
void gpio_set_mode(uint16_t pin, GPIO_MODE mode); void gpio_set_mode(uint16_t pin, GPIO_MODE mode);
void gpio_set_af(uint16_t pin, uint8_t af);
void gpio_write(uint16_t pin, void gpio_write(uint16_t pin,
# 72 "src/gpio.h" 3 4 # 47 "src/gpio.h" 3 4
_Bool _Bool
# 72 "src/gpio.h" # 47 "src/gpio.h"
val); val);
# 6 "src/main.c" 2 # 6 "src/main.c" 2
# 1 "src/flash.h" 1 # 1 "src/flash.h" 1
@@ -2239,7 +2200,7 @@ struct flash {
#define FLASH_ACR_ICEN_ENABLE (1 <<FLASH_ACR_ICEN_BIT) #define FLASH_ACR_ICEN_ENABLE (1 <<FLASH_ACR_ICEN_BIT)
#define FLASH_ACR_LATENCY_3_WAIT_STATES (0x0111) #define FLASH_ACR_LATENCY_3_WAIT_STATES (0b0011)
#define FLASH_ACR_LATENCY_BIT 0 #define FLASH_ACR_LATENCY_BIT 0
#define FLASH_ACR_LATENCY_MASK (0b1111) #define FLASH_ACR_LATENCY_MASK (0b1111)
@@ -2326,24 +2287,11 @@ struct usart {
#define USART_SR_TXE_BIT 7
#define USART_SR_TXE_TRANSMITTED (1 << USART_SR_TXE_BIT)
#define USART_SR_TC_BIT 6 #define USART_SR_TC_BIT 6
#define USART_SR_TC_COMPLETED (1 << USART_SR_TC_BIT) #define USART_SR_TC_COMPLETED (1 << USART_SR_TC_BIT)
#define USART_SR_RXNE_BIT 5
#define USART_SR_RXNE_READY (1 <<USART_SR_RXNE_BIT)
#define USART_CR1_OVER8_BIT 15
#define USART_CR1_OVER8_8 (1 << USART_CR1_OVER8_BIT)
#define USART_CR1_UE_BIT 13 #define USART_CR1_UE_BIT 13
#define USART_CR1_UE_ENABLE (1 << USART_CR1_UE_BIT) #define USART_CR1_UE_ENABLE (1 << USART_CR1_UE_BIT)
@@ -2381,13 +2329,11 @@ static void system_clock_init(void) {
((struct rcc *) (0x40023800U))->CR &= ~(1 << 0); ((struct rcc *) (0x40023800U))->CR &= ~(1 << 0);
# 34 "src/main.c"
((struct rcc *) (0x40023800U))->CR |= (1 << 16); ((struct rcc *) (0x40023800U))->CR |= (1 << 16);
((struct rcc *) (0x40023800U))->CR |= (1 << 19);
while (!(((struct rcc *) (0x40023800U))->CR & (1 << 17))); while (!(((struct rcc *) (0x40023800U))->CR & (1 << 17)));
@@ -2396,7 +2342,6 @@ static void system_clock_init(void) {
((struct rcc *) (0x40023800U))->CR &= ~(1 << 24); ((struct rcc *) (0x40023800U))->CR &= ~(1 << 24);
((struct rcc *) (0x40023800U))->PLLCFGR |= (1 << 22); ((struct rcc *) (0x40023800U))->PLLCFGR |= (1 << 22);
@@ -2452,13 +2397,13 @@ int main(void) {
uint16_t counter = ((struct timer *) (0x40000800U))->CNT; uint16_t counter = ((struct timer *) (0x40000800U))->CNT;
# 103 "src/main.c" 3 4 # 90 "src/main.c" 3 4
_Bool _Bool
# 103 "src/main.c" # 90 "src/main.c"
led_on = led_on =
# 103 "src/main.c" 3 4 # 90 "src/main.c" 3 4
((_Bool)+0u) ((_Bool)+0u)
# 103 "src/main.c" # 90 "src/main.c"
; ;
while(1) { while(1) {
if ((((struct timer *) (0x40000800U))->CNT - counter) >= 250) { if ((((struct timer *) (0x40000800U))->CNT - counter) >= 250) {
build/main.o
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build/timer.S
+215 -255
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build/timer.i
-14
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@@ -2014,11 +2014,6 @@ struct rcc {
#define RCC_CR_PLLON_ON (1 << RCC_CR_PLLON_BIT) #define RCC_CR_PLLON_ON (1 << RCC_CR_PLLON_BIT)
#define RCC_CR_CSS_BIT 19
#define RCC_CR_CSS_ON (1 << RCC_CR_CSS_BIT)
#define RCC_CR_HSERDY_BIT 17 #define RCC_CR_HSERDY_BIT 17
#define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT) #define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT)
@@ -2041,7 +2036,6 @@ struct rcc {
#define RCC_PLLCFGR_PLLSRC_BIT 22 #define RCC_PLLCFGR_PLLSRC_BIT 22
#define RCC_PLLCFGR_PLLSRC_HSE (1 << RCC_PLLCFGR_PLLSRC_BIT) #define RCC_PLLCFGR_PLLSRC_HSE (1 << RCC_PLLCFGR_PLLSRC_BIT)
#define RCC_PLLCFGR_PLLSRC_HSI (0 << RCC_PLLCFGR_PLLSRC_BIT)
#define RCC_PLLCFGR_PLLP_BIT 16 #define RCC_PLLCFGR_PLLP_BIT 16
#define RCC_PLLCFGR_PLLP_MASK (0b11) #define RCC_PLLCFGR_PLLP_MASK (0b11)
@@ -2061,14 +2055,12 @@ struct rcc {
#define RCC_CFGR_PPRE_DIV_2 (0b100) #define RCC_CFGR_PPRE_DIV_2 (0b100)
#define RCC_CFGR_MCO1_HSI (0b00)
#define RCC_CFGR_MCO1_HSE (0b10) #define RCC_CFGR_MCO1_HSE (0b10)
#define RCC_CFGR_MCO1_PLL (0b11) #define RCC_CFGR_MCO1_PLL (0b11)
#define RCC_CFGR_MCO1_BIT 21 #define RCC_CFGR_MCO1_BIT 21
#define RCC_CFGR_MCO1_MASK (0b11) #define RCC_CFGR_MCO1_MASK (0b11)
#define RCC_CFGR_MCO1PRE_DIV5 (0b111)
#define RCC_CFGR_MCO1PRE_DIV4 (0b110) #define RCC_CFGR_MCO1PRE_DIV4 (0b110)
#define RCC_CFGR_MCO1PRE_DIV2 (0b100) #define RCC_CFGR_MCO1PRE_DIV2 (0b100)
@@ -2096,7 +2088,6 @@ struct rcc {
#define RCC_CFGR_SWS_MASK (0b11) #define RCC_CFGR_SWS_MASK (0b11)
#define RCC_CFGR_SW_PLL (0b10)
#define RCC_CFGR_SW_PLL (0b10) #define RCC_CFGR_SW_PLL (0b10)
#define RCC_CFGR_SW_BIT 0 #define RCC_CFGR_SW_BIT 0
@@ -2104,11 +2095,6 @@ struct rcc {
#define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT) #define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT)
#define RCC_AHB1ENR_GPIOAEN_BIT 0
#define RCC_AHB1ENR_GPIOAEN_ENABLE (1 << RCC_AHB1ENR_GPIOAEN_BIT)
#define RCC_APB1ENR_PWREN_BIT 28 #define RCC_APB1ENR_PWREN_BIT 28
#define RCC_APB1ENR_PWREN_CLOCK_ENABLE (1 << RCC_APB1ENR_PWREN_BIT) #define RCC_APB1ENR_PWREN_CLOCK_ENABLE (1 << RCC_APB1ENR_PWREN_BIT)
build/timer.o
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build/usart.S
+757 -826
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build/usart.i
+22 -86
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@@ -2014,11 +2014,6 @@ struct rcc {
#define RCC_CR_PLLON_ON (1 << RCC_CR_PLLON_BIT) #define RCC_CR_PLLON_ON (1 << RCC_CR_PLLON_BIT)
#define RCC_CR_CSS_BIT 19
#define RCC_CR_CSS_ON (1 << RCC_CR_CSS_BIT)
#define RCC_CR_HSERDY_BIT 17 #define RCC_CR_HSERDY_BIT 17
#define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT) #define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT)
@@ -2041,7 +2036,6 @@ struct rcc {
#define RCC_PLLCFGR_PLLSRC_BIT 22 #define RCC_PLLCFGR_PLLSRC_BIT 22
#define RCC_PLLCFGR_PLLSRC_HSE (1 << RCC_PLLCFGR_PLLSRC_BIT) #define RCC_PLLCFGR_PLLSRC_HSE (1 << RCC_PLLCFGR_PLLSRC_BIT)
#define RCC_PLLCFGR_PLLSRC_HSI (0 << RCC_PLLCFGR_PLLSRC_BIT)
#define RCC_PLLCFGR_PLLP_BIT 16 #define RCC_PLLCFGR_PLLP_BIT 16
#define RCC_PLLCFGR_PLLP_MASK (0b11) #define RCC_PLLCFGR_PLLP_MASK (0b11)
@@ -2061,14 +2055,12 @@ struct rcc {
#define RCC_CFGR_PPRE_DIV_2 (0b100) #define RCC_CFGR_PPRE_DIV_2 (0b100)
#define RCC_CFGR_MCO1_HSI (0b00)
#define RCC_CFGR_MCO1_HSE (0b10) #define RCC_CFGR_MCO1_HSE (0b10)
#define RCC_CFGR_MCO1_PLL (0b11) #define RCC_CFGR_MCO1_PLL (0b11)
#define RCC_CFGR_MCO1_BIT 21 #define RCC_CFGR_MCO1_BIT 21
#define RCC_CFGR_MCO1_MASK (0b11) #define RCC_CFGR_MCO1_MASK (0b11)
#define RCC_CFGR_MCO1PRE_DIV5 (0b111)
#define RCC_CFGR_MCO1PRE_DIV4 (0b110) #define RCC_CFGR_MCO1PRE_DIV4 (0b110)
#define RCC_CFGR_MCO1PRE_DIV2 (0b100) #define RCC_CFGR_MCO1PRE_DIV2 (0b100)
@@ -2096,7 +2088,6 @@ struct rcc {
#define RCC_CFGR_SWS_MASK (0b11) #define RCC_CFGR_SWS_MASK (0b11)
#define RCC_CFGR_SW_PLL (0b10)
#define RCC_CFGR_SW_PLL (0b10) #define RCC_CFGR_SW_PLL (0b10)
#define RCC_CFGR_SW_BIT 0 #define RCC_CFGR_SW_BIT 0
@@ -2104,11 +2095,6 @@ struct rcc {
#define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT) #define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT)
#define RCC_AHB1ENR_GPIOAEN_BIT 0
#define RCC_AHB1ENR_GPIOAEN_ENABLE (1 << RCC_AHB1ENR_GPIOAEN_BIT)
#define RCC_APB1ENR_PWREN_BIT 28 #define RCC_APB1ENR_PWREN_BIT 28
#define RCC_APB1ENR_PWREN_CLOCK_ENABLE (1 << RCC_APB1ENR_PWREN_BIT) #define RCC_APB1ENR_PWREN_CLOCK_ENABLE (1 << RCC_APB1ENR_PWREN_BIT)
@@ -2150,45 +2136,19 @@ struct gpio {
volatile uint32_t AFRH; volatile uint32_t AFRH;
}; };
#define GPIOA_BASE_ADDR (0x40020000U)
#define GPIOA ((struct gpio *) GPIOA_BASE_ADDR)
#define GPIO_MODER_AF_MODE (0b10)
#define GPIO_MODER_MODER8_BIT 16
#define GPIO_MODER_MODER8_MASK (0b11)
#define GPIO_MODER_MODER3_BIT 6
#define GPIO_MODER_MODER3_MASK (0b11)
#define GPIO_MODER_MODER2_BIT 4
#define GPIO_MODER_MODER2_MASK (0b11)
#define GPIO_AFRH_AFRH8_BIT 0
#define GPIO_AFRH_AFRH8_MASK (0b1111)
#define GPIO_AFRH_AFRH8_MCO_1 (0b0000)
#define GPIO_AFRL_AFRL3_BIT 12
#define GPIO_AFRL_AFRL3_MASK (0b1111)
#define GPIO_AFRL_AFRL3_USART2_RX (0b0111)
#define GPIO_AFRL_AFRL2_BIT 8
#define GPIO_AFRL_AFRL2_MASK (0b1111)
#define GPIO_AFRL_AFRL2_USART2_TX (0b0111)
#define GPIO_AF_MCO_1 (0b0000)
#define GPIO_AF_USART2_RX (0b0111)
#define GPIO_AF_USART2_TX (0b0111)
#define GPIO_BASE_ADDR (0x40020000U) #define GPIO_BASE_ADDR (0x40020000U)
#define GPIO_PORT_OFFSET (0x400U) #define GPIO_PORT_OFFSET (0x400U)
#define GPIO(port) ((struct gpio*)(uintptr_t)(GPIO_BASE_ADDR + (GPIO_PORT_OFFSET * port))) #define GPIO(port) ((struct gpio*)(uintptr_t)(GPIO_BASE_ADDR + (GPIO_PORT_OFFSET * port)))
#define BIT(x) (1 << x)
#define PIN(port,num) ((((port) - 'A') << 8) | num) #define PORT(port) (((port) - 'A') << 8)
#define PIN(port,num) (PORT(port) | num)
#define PINNUM(pin) (pin & 0b1111) #define PINNUM(pin) (pin & 0b1111)
@@ -2202,10 +2162,11 @@ typedef enum {
} GPIO_MODE; } GPIO_MODE;
void gpio_set_mode(uint16_t pin, GPIO_MODE mode); void gpio_set_mode(uint16_t pin, GPIO_MODE mode);
void gpio_set_af(uint16_t pin, uint8_t af);
void gpio_write(uint16_t pin, void gpio_write(uint16_t pin,
# 72 "src/gpio.h" 3 4 # 47 "src/gpio.h" 3 4
_Bool _Bool
# 72 "src/gpio.h" # 47 "src/gpio.h"
val); val);
# 3 "src/usart.c" 2 # 3 "src/usart.c" 2
# 1 "src/usart.h" 1 # 1 "src/usart.h" 1
@@ -2229,24 +2190,11 @@ struct usart {
#define USART_SR_TXE_BIT 7
#define USART_SR_TXE_TRANSMITTED (1 << USART_SR_TXE_BIT)
#define USART_SR_TC_BIT 6 #define USART_SR_TC_BIT 6
#define USART_SR_TC_COMPLETED (1 << USART_SR_TC_BIT) #define USART_SR_TC_COMPLETED (1 << USART_SR_TC_BIT)
#define USART_SR_RXNE_BIT 5
#define USART_SR_RXNE_READY (1 <<USART_SR_RXNE_BIT)
#define USART_CR1_OVER8_BIT 15
#define USART_CR1_OVER8_8 (1 << USART_CR1_OVER8_BIT)
#define USART_CR1_UE_BIT 13 #define USART_CR1_UE_BIT 13
#define USART_CR1_UE_ENABLE (1 << USART_CR1_UE_BIT) #define USART_CR1_UE_ENABLE (1 << USART_CR1_UE_BIT)
@@ -2274,38 +2222,28 @@ void usart2_write(char *buf);
void usart2_init(void) { void usart2_init(void) {
((struct rcc *) (0x40023800U))->AHB1ENR |= (1 << 0); ((struct rcc *) (0x40023800U))->AHB1ENR |= (1 << ((('A') - 'A') << 8));
uint16_t txPin = (((('A') - 'A') << 8) | 2);
gpio_set_mode(txPin, GPIO_MODE_AF);
gpio_set_af(txPin, (0b0111));
((struct gpio *) (0x40020000U))->MODER &= ~((0b11) << 4); uint16_t rxPin = (((('A') - 'A') << 8) | 3);
((struct gpio *) (0x40020000U))->MODER |= ((0b10) << 4); gpio_set_mode(rxPin, GPIO_MODE_AF);
((struct gpio *) (0x40020000U))->MODER &= ~((0b11) << 6); gpio_set_af(rxPin, (0b0111));
((struct gpio *) (0x40020000U))->MODER |= ((0b10) << 6); # 29 "src/usart.c"
((struct gpio *) (0x40020000U))->AFRL &= ~((0b1111) << 8);
((struct gpio *) (0x40020000U))->AFRL |= ((0b0111) << 8);
((struct gpio *) (0x40020000U))->AFRL &= ~((0b1111) << 12);
((struct gpio *) (0x40020000U))->AFRL |= ((0b0111) << 12);
((struct gpio *) (0x40020000U))->MODER &= ~((0b11) << 16);
((struct gpio *) (0x40020000U))->MODER |= ((0b10) << 16);
((struct gpio *) (0x40020000U))->AFRH &= ~((0b1111) << 0);
((struct gpio *) (0x40020000U))->AFRH |= ((0b0000) << 0);
((struct rcc *) (0x40023800U))->APB1ENR |= (1 << 17); ((struct rcc *) (0x40023800U))->APB1ENR |= (1 << 17);
((struct usart *) (0x40004400U))->CR1 = 0; ((struct usart *) (0x40004400U))->CR1 = 0;
((struct usart *) (0x40004400U))->CR2 = 0; ((struct usart *) (0x40004400U))->CR2 = 0;
((struct usart *) (0x40004400U))->CR3 = 0; ((struct usart *) (0x40004400U))->CR3 = 0;
# 71 "src/usart.c" # 52 "src/usart.c"
((struct usart *) (0x40004400U))->BRR |= 417; ((struct usart *) (0x40004400U))->BRR &= ~((0b111111111111) << 4);
((struct usart *) (0x40004400U))->BRR |= (0x1A << 4);
((struct usart *) (0x40004400U))->BRR &= ~((0b111) << 0);
((struct usart *) (0x40004400U))->BRR |= (0x0 << 4);
((struct usart *) (0x40004400U))->CR1 |= (1 << 3); ((struct usart *) (0x40004400U))->CR1 |= (1 << 3);
@@ -2317,11 +2255,9 @@ void usart2_start(void) {
} }
void usart2_write_byte(uint8_t c) { void usart2_write_byte(uint8_t c) {
((struct usart *) (0x40004400U))->DR = c; ((struct usart *) (0x40004400U))->DR = c;
while (!(((struct usart *) (0x40004400U))->SR & (1 << 6))); while (!(((struct usart *) (0x40004400U))->SR & (1 << 6)));
} }
build/usart.o
BIN
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Binary file not shown.
flake.nix
+1 -1
View File
@@ -32,8 +32,8 @@
pkgs.stlink pkgs.stlink
pkgs.gdb pkgs.gdb
pkgs.openocd pkgs.openocd
pkgs.stm32cubemx
pkgs.gdbgui pkgs.gdbgui
pkgs.stm32cubemx
]; ];
}; };
} }
src/flash.h
+1 -1
View File
@@ -25,7 +25,7 @@ struct flash {
#define FLASH_ACR_ICEN_ENABLE (1 <<FLASH_ACR_ICEN_BIT) #define FLASH_ACR_ICEN_ENABLE (1 <<FLASH_ACR_ICEN_BIT)
// Latency // Latency
#define FLASH_ACR_LATENCY_3_WAIT_STATES (0x0111) #define FLASH_ACR_LATENCY_3_WAIT_STATES (0b0011)
#define FLASH_ACR_LATENCY_BIT 0 // Bits [3:0] #define FLASH_ACR_LATENCY_BIT 0 // Bits [3:0]
#define FLASH_ACR_LATENCY_MASK (0b1111) #define FLASH_ACR_LATENCY_MASK (0b1111)
src/gpio.c
+14 -2
View File
@@ -6,8 +6,20 @@
void gpio_set_mode(uint16_t pin, GPIO_MODE mode) { void gpio_set_mode(uint16_t pin, GPIO_MODE mode) {
struct gpio *gpio = GPIO(PINPORT(pin)); // GPIO port address struct gpio *gpio = GPIO(PINPORT(pin)); // GPIO port address
int pn = PINNUM(pin); // Pin number int pn = PINNUM(pin); // Pin number
gpio->MODER &= ~(0x0011 << (pn * 2)); // Clear existing setting. Each pin uses 2 bits gpio->MODER &= ~(0b11 << (pn * 2)); // Clear existing setting. Each pin uses 2 bits
gpio->MODER |= (mode & 0b011) << (pn * 2); // Set new mode. Each pin uses 2 bits gpio->MODER |= (mode & 0b11) << (pn * 2); // Set new mode. Each pin uses 2 bits
}
void gpio_set_af(uint16_t pin, uint8_t af) {
struct gpio *gpio = GPIO(PINPORT(pin));
int pn = PINNUM(pin);
if (pn < 8) {
gpio->AFRL &= ~(0b1111 << (pn * 4)); // Each pin uses 4 bits
gpio->AFRL |= (af & 0b1111) << (pn * 4);
} else {
gpio->AFRH &= ~(0b1111 << (pn * 4)); // Each pin uses 4 bits
gpio->AFRH |= (af & 0b1111) << (pn * 4);
}
} }
void gpio_write(uint16_t pin, bool val) { void gpio_write(uint16_t pin, bool val) {
src/gpio.h
+8 -33
View File
@@ -17,45 +17,19 @@ struct gpio {
volatile uint32_t AFRH; // Alternative function high register volatile uint32_t AFRH; // Alternative function high register
}; };
#define GPIOA_BASE_ADDR (0x40020000U) // AFRH, AFRL registers
#define GPIOA ((struct gpio *) GPIOA_BASE_ADDR) #define GPIO_AF_MCO_1 (0b0000) // Alternative function 0 (AF0)
#define GPIO_AF_USART2_RX (0b0111) // Alternative function 7 (AF7)
#define GPIO_AF_USART2_TX (0b0111) // Alternative function 7 (AF7)
// MODER register
#define GPIO_MODER_AF_MODE (0b10)
#define GPIO_MODER_MODER8_BIT 16 // Bits [17:16]
#define GPIO_MODER_MODER8_MASK (0b11)
#define GPIO_MODER_MODER3_BIT 6 // Bits [7:6]
#define GPIO_MODER_MODER3_MASK (0b11)
#define GPIO_MODER_MODER2_BIT 4 // Bits [5:4]
#define GPIO_MODER_MODER2_MASK (0b11)
// AFRH register
#define GPIO_AFRH_AFRH8_BIT 0 // Bits [3:0]
#define GPIO_AFRH_AFRH8_MASK (0b1111)
#define GPIO_AFRH_AFRH8_MCO_1 (0b0000) // Alternative function 0 (AF0)
// AFRL register
#define GPIO_AFRL_AFRL3_BIT 12 // Bits [15:12]
#define GPIO_AFRL_AFRL3_MASK (0b1111)
#define GPIO_AFRL_AFRL3_USART2_RX (0b0111) // Alternative function 7 (AF7)
#define GPIO_AFRL_AFRL2_BIT 8 // Bits [11:8]
#define GPIO_AFRL_AFRL2_MASK (0b1111)
#define GPIO_AFRL_AFRL2_USART2_TX (0b0111) // Alternative function 7 (AF7)
// TODO did I intend to remove GPIO, BIT, PIN etc below with GPIOA, GPIOB etc?
#define GPIO_BASE_ADDR (0x40020000U) #define GPIO_BASE_ADDR (0x40020000U)
#define GPIO_PORT_OFFSET (0x400U) #define GPIO_PORT_OFFSET (0x400U)
#define GPIO(port) ((struct gpio*)(uintptr_t)(GPIO_BASE_ADDR + (GPIO_PORT_OFFSET * port))) #define GPIO(port) ((struct gpio*)(uintptr_t)(GPIO_BASE_ADDR + (GPIO_PORT_OFFSET * port)))
#define BIT(x) (1 << x) // Create a 8bit number from a port
#define PORT(port) (((port) - 'A') << 8)
// Create a 16bit number from a port and pin // Create a 16bit number from a port and pin
#define PIN(port, num) ((((port) - 'A') << 8) | num) #define PIN(port, num) (PORT(port) | num)
// get the lower byte from a PIN // get the lower byte from a PIN
#define PINNUM(pin) (pin & 0b1111) #define PINNUM(pin) (pin & 0b1111)
// get the upper byte from a PIN // get the upper byte from a PIN
@@ -69,6 +43,7 @@ typedef enum {
} GPIO_MODE; } GPIO_MODE;
void gpio_set_mode(uint16_t pin, GPIO_MODE mode); void gpio_set_mode(uint16_t pin, GPIO_MODE mode);
void gpio_set_af(uint16_t pin, uint8_t af);
void gpio_write(uint16_t pin, bool val); void gpio_write(uint16_t pin, bool val);
#endif #endif
src/main.c
+2 -15
View File
@@ -21,21 +21,9 @@ static void system_clock_init(void) {
// Turn off HSI (which is on by default) // Turn off HSI (which is on by default)
RCC->CR &= ~RCC_CR_HSION_ON; RCC->CR &= ~RCC_CR_HSION_ON;
// Output HSE clock
/* RCC->CFGR &= ~(RCC_CFGR_MCO1_MASK << RCC_CFGR_MCO1_BIT); */
/* RCC->CFGR |= (RCC_CFGR_MCO1_HSE << RCC_CFGR_MCO1_BIT); */
/* RCC->CFGR |= (RCC_CFGR_MCO1_PLL << RCC_CFGR_MCO1_BIT); */
/* RCC->CFGR |= (RCC_CFGR_MCO1_HSI << RCC_CFGR_MCO1_BIT); */
/* RCC->CFGR &= ~(RCC_CFGR_MCO1PRE_MASK << RCC_CFGR_MCO1PRE_BIT); */
/* RCC->CFGR |= (RCC_CFGR_MCO1PRE_DIV4 << RCC_CFGR_MCO1PRE_BIT); */
// Turn on HSE // Turn on HSE
RCC->CR |= RCC_CR_HSEON_ON; RCC->CR |= RCC_CR_HSEON_ON;
// Turn on clock security system
RCC->CR |= RCC_CR_CSS_ON;
// Wait indefinitely for HSE to be ready // Wait indefinitely for HSE to be ready
// TODO indicate error/timeout somehow? // TODO indicate error/timeout somehow?
while (!(RCC->CR & RCC_CR_HSERDY_READY)); while (!(RCC->CR & RCC_CR_HSERDY_READY));
@@ -45,7 +33,6 @@ static void system_clock_init(void) {
RCC->CR &= ~RCC_CR_PLLON_ON; RCC->CR &= ~RCC_CR_PLLON_ON;
// Set HSE as PLL source // Set HSE as PLL source
/* RCC->PLLCFGR |= RCC_PLLCFGR_PLLSRC_HSE; */
RCC->PLLCFGR |= RCC_PLLCFGR_PLLSRC_HSE; RCC->PLLCFGR |= RCC_PLLCFGR_PLLSRC_HSE;
// Settings to achieve system clock of 96Mhz // Settings to achieve system clock of 96Mhz
@@ -74,7 +61,7 @@ static void system_clock_init(void) {
FLASH->ACR |= FLASH_ACR_DCEN_ENABLE; FLASH->ACR |= FLASH_ACR_DCEN_ENABLE;
FLASH->ACR |= FLASH_ACR_ICEN_ENABLE; FLASH->ACR |= FLASH_ACR_ICEN_ENABLE;
// TODO breaks with these flash settings on; what were they intended to do? // TODO breaks with these flash settings on; turning off for now
// Set latency to be 3 wait states (TODO: understand why exactly 3) // Set latency to be 3 wait states (TODO: understand why exactly 3)
/* FLASH->ACR &= ~(FLASH_ACR_LATENCY_MASK << FLASH_ACR_LATENCY_BIT); */ /* FLASH->ACR &= ~(FLASH_ACR_LATENCY_MASK << FLASH_ACR_LATENCY_BIT); */
/* RCC->CFGR |= (FLASH_ACR_LATENCY_3_WAIT_STATES << FLASH_ACR_LATENCY_BIT); */ /* RCC->CFGR |= (FLASH_ACR_LATENCY_3_WAIT_STATES << FLASH_ACR_LATENCY_BIT); */
@@ -96,7 +83,7 @@ int main(void) {
(void) usart2_start(); (void) usart2_start();
uint16_t led = PIN('C', 13); // Blue LED uint16_t led = PIN('C', 13); // Blue LED
RCC->AHB1ENR |= BIT(PINPORT(led)); // Enable GPIO clock for LED RCC->AHB1ENR |= (1 << PINPORT(led)); // Enable GPIO clock for LED
gpio_set_mode(led, GPIO_MODE_OUTPUT); // Set blue LED to output mode gpio_set_mode(led, GPIO_MODE_OUTPUT); // Set blue LED to output mode
uint16_t counter = TIM4->CNT; uint16_t counter = TIM4->CNT;
src/rcc.h
-14
View File
@@ -46,11 +46,6 @@ struct rcc {
#define RCC_CR_PLLON_BIT 24 #define RCC_CR_PLLON_BIT 24
#define RCC_CR_PLLON_ON (1 << RCC_CR_PLLON_BIT) #define RCC_CR_PLLON_ON (1 << RCC_CR_PLLON_BIT)
// Clock security system
#define RCC_CR_CSS_BIT 19
#define RCC_CR_CSS_ON (1 << RCC_CR_CSS_BIT)
// HSE clock ready flag // HSE clock ready flag
#define RCC_CR_HSERDY_BIT 17 #define RCC_CR_HSERDY_BIT 17
#define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT) #define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT)
@@ -74,7 +69,6 @@ struct rcc {
#define RCC_PLLCFGR_PLLSRC_BIT 22 #define RCC_PLLCFGR_PLLSRC_BIT 22
#define RCC_PLLCFGR_PLLSRC_HSE (1 << RCC_PLLCFGR_PLLSRC_BIT) #define RCC_PLLCFGR_PLLSRC_HSE (1 << RCC_PLLCFGR_PLLSRC_BIT)
#define RCC_PLLCFGR_PLLSRC_HSI (0 << RCC_PLLCFGR_PLLSRC_BIT)
#define RCC_PLLCFGR_PLLP_BIT 16 // Bits [17:16] #define RCC_PLLCFGR_PLLP_BIT 16 // Bits [17:16]
#define RCC_PLLCFGR_PLLP_MASK (0b11) #define RCC_PLLCFGR_PLLP_MASK (0b11)
@@ -94,14 +88,12 @@ struct rcc {
#define RCC_CFGR_PPRE_DIV_2 (0b100) #define RCC_CFGR_PPRE_DIV_2 (0b100)
// Microcontroller clock output 1 // Microcontroller clock output 1
#define RCC_CFGR_MCO1_HSI (0b00)
#define RCC_CFGR_MCO1_HSE (0b10) #define RCC_CFGR_MCO1_HSE (0b10)
#define RCC_CFGR_MCO1_PLL (0b11) #define RCC_CFGR_MCO1_PLL (0b11)
#define RCC_CFGR_MCO1_BIT 21 // Bits [22:21] #define RCC_CFGR_MCO1_BIT 21 // Bits [22:21]
#define RCC_CFGR_MCO1_MASK (0b11) #define RCC_CFGR_MCO1_MASK (0b11)
#define RCC_CFGR_MCO1PRE_DIV5 (0b111)
#define RCC_CFGR_MCO1PRE_DIV4 (0b110) #define RCC_CFGR_MCO1PRE_DIV4 (0b110)
#define RCC_CFGR_MCO1PRE_DIV2 (0b100) #define RCC_CFGR_MCO1PRE_DIV2 (0b100)
@@ -130,17 +122,11 @@ struct rcc {
// System clock switch // System clock switch
#define RCC_CFGR_SW_PLL (0b10) #define RCC_CFGR_SW_PLL (0b10)
#define RCC_CFGR_SW_PLL (0b10)
#define RCC_CFGR_SW_BIT 0 // Bits [1:0] #define RCC_CFGR_SW_BIT 0 // Bits [1:0]
#define RCC_CFGR_SW_MASK (0b11) #define RCC_CFGR_SW_MASK (0b11)
#define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT) #define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT)
// AHB1ENR Register
// GPIOA AHB1ENR
#define RCC_AHB1ENR_GPIOAEN_BIT 0
#define RCC_AHB1ENR_GPIOAEN_ENABLE (1 << RCC_AHB1ENR_GPIOAEN_BIT)
// APB1ENR Register // APB1ENR Register
#define RCC_APB1ENR_PWREN_BIT 28 #define RCC_APB1ENR_PWREN_BIT 28
#define RCC_APB1ENR_PWREN_CLOCK_ENABLE (1 << RCC_APB1ENR_PWREN_BIT) #define RCC_APB1ENR_PWREN_CLOCK_ENABLE (1 << RCC_APB1ENR_PWREN_BIT)
src/usart.c
+26 -44
View File
@@ -3,29 +3,27 @@
#include "usart.h" #include "usart.h"
void usart2_init(void) { void usart2_init(void) {
// Enable clock for GPIOA // Enable clock for GPIOA as USART2 is on PORT A pins
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN_ENABLE; RCC->AHB1ENR |= (1 << PORT('A'));
// Configure PA2 and PA3 (USART2 pins) to use alternative functions // Configure PA2 and PA3 (USART2 pins) to use alternative functions
// file:///home/alex/sync/org/stm32-sand/stm32f411ce.pdf#page=48 uint16_t txPin = PIN('A', 2);
GPIOA->MODER &= ~(GPIO_MODER_MODER2_MASK << GPIO_MODER_MODER2_BIT); gpio_set_mode(txPin, GPIO_MODE_AF);
GPIOA->MODER |= (GPIO_MODER_AF_MODE << GPIO_MODER_MODER2_BIT); gpio_set_af(txPin, GPIO_AF_USART2_TX);
GPIOA->MODER &= ~(GPIO_MODER_MODER3_MASK << GPIO_MODER_MODER3_BIT);
GPIOA->MODER |= (GPIO_MODER_AF_MODE << GPIO_MODER_MODER3_BIT);
// Set pin alternative modes to use USART uint16_t rxPin = PIN('A', 3);
GPIOA->AFRL &= ~(GPIO_AFRL_AFRL2_MASK << GPIO_AFRL_AFRL2_BIT); gpio_set_mode(rxPin, GPIO_MODE_AF);
GPIOA->AFRL |= (GPIO_AFRL_AFRL2_USART2_TX << GPIO_AFRL_AFRL2_BIT); gpio_set_af(rxPin, GPIO_AF_USART2_RX);
GPIOA->AFRL &= ~(GPIO_AFRL_AFRL3_MASK << GPIO_AFRL_AFRL3_BIT);
GPIOA->AFRL |= (GPIO_AFRL_AFRL3_USART2_RX << GPIO_AFRL_AFRL3_BIT);
// Configure PA8 to output HSE (MCO1) // Enable MC01; for debugging
GPIOA->MODER &= ~(GPIO_MODER_MODER8_MASK << GPIO_MODER_MODER8_BIT); /* uint16_t clockOutPin = PIN('A', 8); */
GPIOA->MODER |= (GPIO_MODER_AF_MODE << GPIO_MODER_MODER8_BIT); /* gpio_set_mode(clockOutPin, GPIO_MODE_AF); */
/* gpio_set_af(clockOutPin, GPIO_AF_MCO_1); */
// Set pin alternative mode to use MCO1 /* RCC->CFGR &= ~(RCC_CFGR_MCO1_MASK << RCC_CFGR_MCO1_BIT); */
GPIOA->AFRH &= ~(GPIO_AFRH_AFRH8_MASK << GPIO_AFRH_AFRH8_BIT); /* RCC->CFGR |= (RCC_CFGR_MCO1_HSE << RCC_CFGR_MCO1_BIT); */
GPIOA->AFRH |= (GPIO_AFRH_AFRH8_MCO_1 << GPIO_AFRH_AFRH8_BIT); /* RCC->CFGR |= (RCC_CFGR_MCO1_PLL << RCC_CFGR_MCO1_BIT); */
/* RCC->CFGR &= ~(RCC_CFGR_MCO1PRE_MASK << RCC_CFGR_MCO1PRE_BIT); */
/* RCC->CFGR |= (RCC_CFGR_MCO1PRE_DIV4 << RCC_CFGR_MCO1PRE_BIT); */
// Enable USART // Enable USART
RCC->APB1ENR |= RCC_APB1ENR_USART2EN_ENABLE; RCC->APB1ENR |= RCC_APB1ENR_USART2EN_ENABLE;
@@ -41,34 +39,20 @@ void usart2_init(void) {
// baud * (8 * (2 - OVER8) * USARTDIV) = f_clock => // baud * (8 * (2 - OVER8) * USARTDIV) = f_clock =>
// USARTDIV = (f_clock / (baud * (8 * (2 - OVER8))) // USARTDIV = (f_clock / (baud * (8 * (2 - OVER8)))
// Target Baud rate = 115200, f_clock = 48MHz,OVER8 = 0 // Target Baud rate = 115200, f_clock = 48MHz, OVER8 = 0
// USARTDIV = 48E6 / (115200 * 8 * 2) = 26.0416666
// USARTDIV = (48E6 / (115200 * (8 * 2))) = 26.0416666
// mantissa = 26 = 0x1A // mantissa = 26 = 0x1A
// fraction = 0.041666 * 16 = 0.666656 ~= 1 // fraction = 0.041666 * 16 = 0.666656 ~= 1
// baud = 48E6 / (8 * 2 * 26) = 115384.61538461539 // baud = 48E6 / (8 * 2 * 26) = 115384.61538461539
// error of 0.001% (115384.61538461539 / 115200 ) = 1.001602564102564 // error of 0.16% (115384.61538461539 / 115200 ) = 1.001602564102564
//
// skipping fractional part as error rate is good.
// f_clock = USARTDIV * (baud * (8 * 2) USART2->BRR &= ~(USART_BRR_MANTISSA_MASK << USART_BRR_MANTISSA_BIT);
// f_clock = 26 * 115200 * 16 = 47923200 = 48MHz USART2->BRR |= (0x1A << USART_BRR_MANTISSA_BIT);
USART2->BRR &= ~(USART_BRR_FRACTION_MASK << USART_BRR_FRACTION_BIT);
// fclk = 13 * 115200 * 16 USART2->BRR |= (0x0 << USART_BRR_MANTISSA_BIT);
// Baud = 9600
// USARTDIV = (48E6 / (9600 * (8 * 2))) = 312.5
// mantissa = 312 = 0x138
// fraction = 0.5 * 16 = 8 = 0x8
// BRR = 0x1388
/* USART2->CR1 |= USART_CR1_OVER8_8; */
/* USART2->BRR &= ~(USART_BRR_MANTISSA_MASK << USART_BRR_MANTISSA_BIT); */
/* USART2->BRR |= (0x1A << USART_BRR_MANTISSA_BIT); */
/* USART2->BRR &= ~(USART_BRR_FRACTION_MASK << USART_BRR_FRACTION_BIT); */
USART2->BRR |= 417;
// Enable transmitter and receiver // Enable transmitter and receiver
USART2->CR1 |= USART_CR1_TE_ENABLE; USART2->CR1 |= USART_CR1_TE_ENABLE;
@@ -80,11 +64,9 @@ void usart2_start(void) {
} }
void usart2_write_byte(uint8_t c) { void usart2_write_byte(uint8_t c) {
// Send data
USART2->DR = c; USART2->DR = c;
// Wait indefinitely for transmission to be ready for data // Wait indefinitely for transmission to be ready for data
/* while ((USART2->SR & USART_SR_TXE_TRANSMITTED) == 0); */
while (!(USART2->SR & USART_SR_TC_COMPLETED)); while (!(USART2->SR & USART_SR_TC_COMPLETED));
} }
src/usart.h
+1 -14
View File
@@ -10,31 +10,18 @@ struct usart {
volatile uint32_t CR1; // Control register 1 volatile uint32_t CR1; // Control register 1
volatile uint32_t CR2; // Control register 2 volatile uint32_t CR2; // Control register 2
volatile uint32_t CR3; // Control register 3 volatile uint32_t CR3; // Control register 3
volatile uint32_t GTPR; // Guard time and prescaler registe volatile uint32_t GTPR; // Guard time and prescaler register
}; };
#define USART2_BASE_ADDR (0x40004400U) #define USART2_BASE_ADDR (0x40004400U)
#define USART2 ((struct usart *) USART2_BASE_ADDR) #define USART2 ((struct usart *) USART2_BASE_ADDR)
// SR Register // SR Register
// Transmission data register empty
#define USART_SR_TXE_BIT 7
#define USART_SR_TXE_TRANSMITTED (1 << USART_SR_TXE_BIT)
// Transmission complete // Transmission complete
#define USART_SR_TC_BIT 6 #define USART_SR_TC_BIT 6
#define USART_SR_TC_COMPLETED (1 << USART_SR_TC_BIT) #define USART_SR_TC_COMPLETED (1 << USART_SR_TC_BIT)
// Read data register not empty
#define USART_SR_RXNE_BIT 5
#define USART_SR_RXNE_READY (1 <<USART_SR_RXNE_BIT)
// CR Register // CR Register
// Oversampling mode
#define USART_CR1_OVER8_BIT 15
#define USART_CR1_OVER8_8 (1 << USART_CR1_OVER8_BIT)
// USART enable // USART enable
#define USART_CR1_UE_BIT 13 #define USART_CR1_UE_BIT 13
#define USART_CR1_UE_ENABLE (1 << USART_CR1_UE_BIT) #define USART_CR1_UE_ENABLE (1 << USART_CR1_UE_BIT)
todo.txt
-2
View File
@@ -1,2 +0,0 @@
- implement UART
- implement tim4 interrupt