Compare commits
25 Commits
278d3cfb9d
...
uart
| Author | SHA1 | Date | |
|---|---|---|---|
 Alexander Heldt
|
68f6d98f1f | ||
|
Alexander Heldt
|
4600e8e838 | ||
|
Alexander Heldt
|
1ae81edf57 | ||
|
Alexander Heldt
|
55ee09eab8 | ||
|
Alexander Heldt
|
95455a7161 | ||
|
Alexander Heldt
|
992b3c5b97 | ||
|
Alexander Heldt
|
3f95f00852 | ||
|
Alexander Heldt
|
2a1e3a41da | ||
|
Alexander Heldt
|
152a9ad8a7 | ||
|
Alexander Heldt
|
980b9a2d9b | ||
|
Alexander Heldt
|
3aad7271a1 | ||
|
Alexander Heldt
|
11f469564f | ||
|
Alexander Heldt
|
916d7d9620 | ||
|
Alexander Heldt
|
a63527a997 | ||
|
Alexander Heldt
|
a1c43ad21c | ||
|
Alexander Heldt
|
8f3285072b | ||
|
Alexander Heldt
|
908cfda5b3 | ||
|
Alexander Heldt
|
a3c1de878a | ||
|
Alexander Heldt
|
062a014c7c | ||
|
Alexander Heldt
|
9b131a3c24 | ||
|
Alexander Heldt
|
c84cf622f1 | ||
|
Alexander Heldt
|
d9389b4eb8 | ||
|
Alexander Heldt
|
0fec3d6a6c | ||
|
Alexander Heldt
|
318ed20061 | ||
|
Alexander Heldt
|
271f3a3a64 |
@@ -31,7 +31,7 @@ ASM_FILES := $(patsubst $(BUILD_DIR)/%.i,$(BUILD_DIR)/%.S,$(PREP_FILES))
|
||||
OBJ_FILES := $(patsubst $(BUILD_DIR)/%.S,$(BUILD_DIR)/%.o,$(ASM_FILES))
|
||||
|
||||
.PHONY: build
|
||||
build: builddir preprocess compile assemble $(BUILD_DIR)/$(TARGET).elf
|
||||
build: clean builddir preprocess compile assemble $(BUILD_DIR)/$(TARGET).elf
|
||||
|
||||
$(BUILD_DIR)/$(TARGET).bin: $(BUILD_DIR)/$(TARGET).elf
|
||||
arm-none-eabi-objcopy -O binary $< $@
|
||||
@@ -65,6 +65,18 @@ assemble: compile $(OBJ_FILES)
|
||||
flash: $(BUILD_DIR)/$(TARGET).bin
|
||||
st-flash --reset write $< 0x8000000
|
||||
|
||||
.PHONY: gdb-server
|
||||
gdb-server:
|
||||
sudo openocd -f stlink.cfg -f stm32f4x.cfg
|
||||
|
||||
.PHONY: gdb-client
|
||||
gdb-client:
|
||||
gdb --symbols $(BUILD_DIR)/$(TARGET).elf --init-eval-command="target extended-remote localhost:3333"
|
||||
|
||||
.PHONY: gdb-guiclient
|
||||
gdb-guiclient:
|
||||
gdbgui --gdb-cmd="gdb --init-eval-command='target extended-remote localhost:3333'" $(BUILD_DIR)/$(TARGET).elf
|
||||
|
||||
.PHONY: clean
|
||||
clean:
|
||||
rm -rf $(BUILD_DIR)
|
||||
|
||||
@@ -0,0 +1,35 @@
|
||||
# Falling sand on the STM32F411CE
|
||||
|
||||
## Building
|
||||
Run
|
||||
```sh
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||||
make build
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||||
```
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||||
|
||||
## Probe for the board
|
||||
Run
|
||||
```sh
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||||
st-info --probe
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||||
```
|
||||
|
||||
## Flashing
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||||
Run
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||||
```sh
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||||
make flash
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||||
```
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||||
|
||||
## Debugging
|
||||
|
||||
### `st-info --probe` shows 0KB flash
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||||
```
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||||
> sudo st-info --probe
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||||
Found 1 stlink programmers
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||||
version: V2J43S28
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||||
serial: 0671FF343056363043090732
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||||
flash: 0 (pagesize: 16384) <--- 0KB flash
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||||
sram: 131072
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||||
chipid: 0x431
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||||
dev-type: STM32F411xC_xE
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||||
```
|
||||
This can happen when the flash is locked. One way to unlock it is to erase the entire chip via the
|
||||
Windows application `ST-Link Util`.
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||||
Binary file not shown.
+278
-142
@@ -33,6 +33,10 @@ Discarded input sections
|
||||
.group 0x00000000 0xc build/main.o
|
||||
.group 0x00000000 0xc build/main.o
|
||||
.group 0x00000000 0xc build/main.o
|
||||
.group 0x00000000 0xc build/main.o
|
||||
.group 0x00000000 0xc build/main.o
|
||||
.group 0x00000000 0xc build/main.o
|
||||
.group 0x00000000 0xc build/main.o
|
||||
.text 0x00000000 0x0 build/main.o
|
||||
.data 0x00000000 0x0 build/main.o
|
||||
.bss 0x00000000 0x0 build/main.o
|
||||
@@ -49,6 +53,7 @@ Discarded input sections
|
||||
.debug_macro 0x00000000 0x89 build/main.o
|
||||
.debug_macro 0x00000000 0x4cc build/main.o
|
||||
.debug_macro 0x00000000 0x22 build/main.o
|
||||
.debug_macro 0x00000000 0x46 build/main.o
|
||||
.group 0x00000000 0xc build/startup.o
|
||||
.group 0x00000000 0xc build/startup.o
|
||||
.group 0x00000000 0xc build/startup.o
|
||||
@@ -62,6 +67,70 @@ Discarded input sections
|
||||
.debug_macro 0x00000000 0x103 build/startup.o
|
||||
.debug_macro 0x00000000 0x6a build/startup.o
|
||||
.debug_macro 0x00000000 0x1df build/startup.o
|
||||
.group 0x00000000 0xc build/timer.o
|
||||
.group 0x00000000 0xc build/timer.o
|
||||
.group 0x00000000 0xc build/timer.o
|
||||
.group 0x00000000 0xc build/timer.o
|
||||
.group 0x00000000 0xc build/timer.o
|
||||
.group 0x00000000 0xc build/timer.o
|
||||
.group 0x00000000 0xc build/timer.o
|
||||
.group 0x00000000 0xc build/timer.o
|
||||
.group 0x00000000 0xc build/timer.o
|
||||
.group 0x00000000 0xc build/timer.o
|
||||
.group 0x00000000 0xc build/timer.o
|
||||
.group 0x00000000 0xc build/timer.o
|
||||
.group 0x00000000 0xc build/timer.o
|
||||
.group 0x00000000 0xc build/timer.o
|
||||
.text 0x00000000 0x0 build/timer.o
|
||||
.data 0x00000000 0x0 build/timer.o
|
||||
.bss 0x00000000 0x0 build/timer.o
|
||||
.debug_macro 0x00000000 0x22 build/timer.o
|
||||
.debug_macro 0x00000000 0x75 build/timer.o
|
||||
.debug_macro 0x00000000 0x2a build/timer.o
|
||||
.debug_macro 0x00000000 0x5c build/timer.o
|
||||
.debug_macro 0x00000000 0x3c build/timer.o
|
||||
.debug_macro 0x00000000 0x103 build/timer.o
|
||||
.debug_macro 0x00000000 0x3a build/timer.o
|
||||
.debug_macro 0x00000000 0x57 build/timer.o
|
||||
.debug_macro 0x00000000 0x6a build/timer.o
|
||||
.debug_macro 0x00000000 0x1df build/timer.o
|
||||
.debug_macro 0x00000000 0x89 build/timer.o
|
||||
.debug_macro 0x00000000 0x4cc build/timer.o
|
||||
.debug_macro 0x00000000 0x22 build/timer.o
|
||||
.group 0x00000000 0xc build/usart.o
|
||||
.group 0x00000000 0xc build/usart.o
|
||||
.group 0x00000000 0xc build/usart.o
|
||||
.group 0x00000000 0xc build/usart.o
|
||||
.group 0x00000000 0xc build/usart.o
|
||||
.group 0x00000000 0xc build/usart.o
|
||||
.group 0x00000000 0xc build/usart.o
|
||||
.group 0x00000000 0xc build/usart.o
|
||||
.group 0x00000000 0xc build/usart.o
|
||||
.group 0x00000000 0xc build/usart.o
|
||||
.group 0x00000000 0xc build/usart.o
|
||||
.group 0x00000000 0xc build/usart.o
|
||||
.group 0x00000000 0xc build/usart.o
|
||||
.group 0x00000000 0xc build/usart.o
|
||||
.group 0x00000000 0xc build/usart.o
|
||||
.group 0x00000000 0xc build/usart.o
|
||||
.text 0x00000000 0x0 build/usart.o
|
||||
.data 0x00000000 0x0 build/usart.o
|
||||
.bss 0x00000000 0x0 build/usart.o
|
||||
.debug_macro 0x00000000 0x22 build/usart.o
|
||||
.debug_macro 0x00000000 0x75 build/usart.o
|
||||
.debug_macro 0x00000000 0x2a build/usart.o
|
||||
.debug_macro 0x00000000 0x5c build/usart.o
|
||||
.debug_macro 0x00000000 0x3c build/usart.o
|
||||
.debug_macro 0x00000000 0x103 build/usart.o
|
||||
.debug_macro 0x00000000 0x3a build/usart.o
|
||||
.debug_macro 0x00000000 0x57 build/usart.o
|
||||
.debug_macro 0x00000000 0x6a build/usart.o
|
||||
.debug_macro 0x00000000 0x1df build/usart.o
|
||||
.debug_macro 0x00000000 0x89 build/usart.o
|
||||
.debug_macro 0x00000000 0x4cc build/usart.o
|
||||
.debug_macro 0x00000000 0x167 build/usart.o
|
||||
.debug_macro 0x00000000 0x22 build/usart.o
|
||||
.debug_macro 0x00000000 0x5e build/usart.o
|
||||
|
||||
Memory Configuration
|
||||
|
||||
@@ -77,6 +146,8 @@ LOAD /nix/store/yr89i11mszv2az19r26l372zgaiivj1c-gcc-arm-embedded-12.3.rel1/bin/
|
||||
LOAD build/gpio.o
|
||||
LOAD build/main.o
|
||||
LOAD build/startup.o
|
||||
LOAD build/timer.o
|
||||
LOAD build/usart.o
|
||||
0x20020000 stack_start = (ORIGIN (sram) + LENGTH (sram))
|
||||
|
||||
.isr_vector 0x08000000 0x198
|
||||
@@ -86,118 +157,144 @@ LOAD build/startup.o
|
||||
0x08000000 interrupt_vector_table
|
||||
0x08000198 . = ALIGN (0x4)
|
||||
|
||||
.text 0x08000198 0x1a8
|
||||
.text 0x08000198 0x520
|
||||
0x08000198 . = ALIGN (0x4)
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
.text.gpio_set_mode
|
||||
0x08000198 0x62 build/gpio.o
|
||||
0x08000198 gpio_set_mode
|
||||
.text.gpio_set_af
|
||||
0x080001fa 0x98 build/gpio.o
|
||||
0x080001fa gpio_set_af
|
||||
.text.gpio_write
|
||||
0x080001fa 0x4c build/gpio.o
|
||||
0x080001fa gpio_write
|
||||
.text.spin 0x08000246 0x22 build/main.o
|
||||
.text.main 0x08000268 0x5c build/main.o
|
||||
0x08000268 main
|
||||
0x08000292 0x4c build/gpio.o
|
||||
0x08000292 gpio_write
|
||||
*fill* 0x080002de 0x2
|
||||
.text.system_clock_init
|
||||
0x080002e0 0x11c build/main.o
|
||||
.text.main 0x080003fc 0x9c build/main.o
|
||||
0x080003fc main
|
||||
.text.init_memory
|
||||
0x080002c4 0x64 build/startup.o
|
||||
0x080002c4 init_memory
|
||||
.text.reset 0x08000328 0x10 build/startup.o
|
||||
0x08000328 reset
|
||||
0x08000498 0x64 build/startup.o
|
||||
0x08000498 init_memory
|
||||
.text.reset 0x080004fc 0x10 build/startup.o
|
||||
0x080004fc reset
|
||||
.text.default_handler
|
||||
0x08000338 0x8 build/startup.o
|
||||
0x08000338 exti0
|
||||
0x08000338 debug_monitor
|
||||
0x08000338 rcc
|
||||
0x08000338 x
|
||||
0x08000338 sdio
|
||||
0x08000338 usage_fault
|
||||
0x08000338 tim1_up_tim10
|
||||
0x08000338 usart1
|
||||
0x08000338 i2c3_er
|
||||
0x08000338 spi2
|
||||
0x08000338 dma1_stream1
|
||||
0x08000338 bus_fault
|
||||
0x08000338 spi5
|
||||
0x08000338 exti3
|
||||
0x08000338 dma2_stream5
|
||||
0x08000338 tim2
|
||||
0x08000338 dma1_stream6
|
||||
0x08000338 default_handler
|
||||
0x08000338 i2c1_er
|
||||
0x08000338 hard_fault
|
||||
0x08000338 usart6
|
||||
0x08000338 exti15_10
|
||||
0x08000338 usart2
|
||||
0x08000338 pend_sv
|
||||
0x08000338 i2c1_ev
|
||||
0x08000338 wwdg
|
||||
0x08000338 adc
|
||||
0x08000338 rtc_alarm
|
||||
0x08000338 spi3
|
||||
0x08000338 exti1
|
||||
0x08000338 mem_manage
|
||||
0x08000338 dma2_stream1
|
||||
0x08000338 dma1_stream2
|
||||
0x08000338 dma2_stream3
|
||||
0x08000338 sv_call
|
||||
0x08000338 tim3
|
||||
0x08000338 otg_fs
|
||||
0x08000338 dma1_stream5
|
||||
0x08000338 dma2_stream6
|
||||
0x08000338 flash
|
||||
0x08000338 tamp_stamp
|
||||
0x08000338 i2c3_ev
|
||||
0x08000338 rtc_wkup
|
||||
0x08000338 dma2_stream0
|
||||
0x08000338 pvd
|
||||
0x08000338 fpu
|
||||
0x08000338 exti4
|
||||
0x08000338 exti2
|
||||
0x08000338 spi1
|
||||
0x08000338 dma1_stream0
|
||||
0x08000338 tim1_brk_tim9
|
||||
0x08000338 i2c2_ev
|
||||
0x08000338 otg_fs_wkup
|
||||
0x08000338 spi4
|
||||
0x08000338 dma2_stream2
|
||||
0x08000338 tim1_cc
|
||||
0x08000338 tim1_trg_com_tim11
|
||||
0x08000338 exti9_5
|
||||
0x08000338 dma1_stream3
|
||||
0x08000338 dma2_stream4
|
||||
0x08000338 i2c2_er
|
||||
0x08000338 dma2_stream7
|
||||
0x08000338 dma1_stream7
|
||||
0x08000338 nmi
|
||||
0x08000338 systick
|
||||
0x08000338 tim4
|
||||
0x08000338 tim5
|
||||
0x08000338 dma1_stream4
|
||||
0x0800050c 0x8 build/startup.o
|
||||
0x0800050c exti0
|
||||
0x0800050c debug_monitor
|
||||
0x0800050c rcc
|
||||
0x0800050c x
|
||||
0x0800050c sdio
|
||||
0x0800050c usage_fault
|
||||
0x0800050c tim1_up_tim10
|
||||
0x0800050c usart1
|
||||
0x0800050c i2c3_er
|
||||
0x0800050c spi2
|
||||
0x0800050c dma1_stream1
|
||||
0x0800050c bus_fault
|
||||
0x0800050c spi5
|
||||
0x0800050c exti3
|
||||
0x0800050c dma2_stream5
|
||||
0x0800050c tim2
|
||||
0x0800050c dma1_stream6
|
||||
0x0800050c default_handler
|
||||
0x0800050c i2c1_er
|
||||
0x0800050c hard_fault
|
||||
0x0800050c usart6
|
||||
0x0800050c exti15_10
|
||||
0x0800050c usart2
|
||||
0x0800050c pend_sv
|
||||
0x0800050c i2c1_ev
|
||||
0x0800050c wwdg
|
||||
0x0800050c adc
|
||||
0x0800050c rtc_alarm
|
||||
0x0800050c spi3
|
||||
0x0800050c exti1
|
||||
0x0800050c mem_manage
|
||||
0x0800050c dma2_stream1
|
||||
0x0800050c dma1_stream2
|
||||
0x0800050c dma2_stream3
|
||||
0x0800050c sv_call
|
||||
0x0800050c tim3
|
||||
0x0800050c otg_fs
|
||||
0x0800050c dma1_stream5
|
||||
0x0800050c dma2_stream6
|
||||
0x0800050c flash
|
||||
0x0800050c tamp_stamp
|
||||
0x0800050c i2c3_ev
|
||||
0x0800050c rtc_wkup
|
||||
0x0800050c dma2_stream0
|
||||
0x0800050c pvd
|
||||
0x0800050c fpu
|
||||
0x0800050c exti4
|
||||
0x0800050c exti2
|
||||
0x0800050c spi1
|
||||
0x0800050c dma1_stream0
|
||||
0x0800050c tim1_brk_tim9
|
||||
0x0800050c i2c2_ev
|
||||
0x0800050c otg_fs_wkup
|
||||
0x0800050c spi4
|
||||
0x0800050c dma2_stream2
|
||||
0x0800050c tim1_cc
|
||||
0x0800050c tim1_trg_com_tim11
|
||||
0x0800050c exti9_5
|
||||
0x0800050c dma1_stream3
|
||||
0x0800050c dma2_stream4
|
||||
0x0800050c i2c2_er
|
||||
0x0800050c dma2_stream7
|
||||
0x0800050c dma1_stream7
|
||||
0x0800050c nmi
|
||||
0x0800050c systick
|
||||
0x0800050c tim4
|
||||
0x0800050c tim5
|
||||
0x0800050c dma1_stream4
|
||||
.text.tim4_init
|
||||
0x08000514 0x40 build/timer.o
|
||||
0x08000514 tim4_init
|
||||
.text.tim4_start
|
||||
0x08000554 0x20 build/timer.o
|
||||
0x08000554 tim4_start
|
||||
.text.usart2_init
|
||||
0x08000574 0xb8 build/usart.o
|
||||
0x08000574 usart2_init
|
||||
.text.usart2_start
|
||||
0x0800062c 0x20 build/usart.o
|
||||
0x0800062c usart2_start
|
||||
.text.usart2_write_byte
|
||||
0x0800064c 0x30 build/usart.o
|
||||
0x0800064c usart2_write_byte
|
||||
.text.usart2_write
|
||||
0x0800067c 0x2a build/usart.o
|
||||
0x0800067c usart2_write
|
||||
*(.rodata)
|
||||
*fill* 0x080006a6 0x2
|
||||
.rodata 0x080006a8 0xf build/main.o
|
||||
*(.rodata.*)
|
||||
0x08000340 . = ALIGN (0x4)
|
||||
0x08000340 _data_addr = LOADADDR (.data)
|
||||
0x080006b8 . = ALIGN (0x4)
|
||||
*fill* 0x080006b7 0x1
|
||||
0x080006b8 _data_addr = LOADADDR (.data)
|
||||
|
||||
.glue_7 0x08000340 0x0
|
||||
.glue_7 0x08000340 0x0 linker stubs
|
||||
.glue_7 0x080006b8 0x0
|
||||
.glue_7 0x080006b8 0x0 linker stubs
|
||||
|
||||
.glue_7t 0x08000340 0x0
|
||||
.glue_7t 0x08000340 0x0 linker stubs
|
||||
.glue_7t 0x080006b8 0x0
|
||||
.glue_7t 0x080006b8 0x0 linker stubs
|
||||
|
||||
.vfp11_veneer 0x08000340 0x0
|
||||
.vfp11_veneer 0x08000340 0x0 linker stubs
|
||||
.vfp11_veneer 0x080006b8 0x0
|
||||
.vfp11_veneer 0x080006b8 0x0 linker stubs
|
||||
|
||||
.v4_bx 0x08000340 0x0
|
||||
.v4_bx 0x08000340 0x0 linker stubs
|
||||
.v4_bx 0x080006b8 0x0
|
||||
.v4_bx 0x080006b8 0x0 linker stubs
|
||||
|
||||
.iplt 0x08000340 0x0
|
||||
.iplt 0x08000340 0x0 build/main.o
|
||||
.iplt 0x080006b8 0x0
|
||||
.iplt 0x080006b8 0x0 build/main.o
|
||||
|
||||
.rel.dyn 0x08000340 0x0
|
||||
.rel.iplt 0x08000340 0x0 build/main.o
|
||||
.rel.dyn 0x080006b8 0x0
|
||||
.rel.iplt 0x080006b8 0x0 build/main.o
|
||||
|
||||
.data 0x20000000 0x0 load address 0x08000340
|
||||
.data 0x20000000 0x0 load address 0x080006b8
|
||||
0x20000000 . = ALIGN (0x4)
|
||||
0x20000000 _data_start = .
|
||||
*(.data)
|
||||
@@ -205,10 +302,10 @@ LOAD build/startup.o
|
||||
0x20000000 . = ALIGN (0x4)
|
||||
0x20000000 _data_end = .
|
||||
|
||||
.igot.plt 0x20000000 0x0 load address 0x08000340
|
||||
.igot.plt 0x20000000 0x0 load address 0x080006b8
|
||||
.igot.plt 0x20000000 0x0 build/main.o
|
||||
|
||||
.bss 0x20000000 0x0 load address 0x08000340
|
||||
.bss 0x20000000 0x0 load address 0x080006b8
|
||||
0x20000000 . = ALIGN (0x4)
|
||||
0x20000000 _bss_start = .
|
||||
*(.bss)
|
||||
@@ -218,34 +315,46 @@ LOAD build/startup.o
|
||||
OUTPUT(build/final.elf elf32-littlearm)
|
||||
LOAD linker stubs
|
||||
|
||||
.debug_info 0x00000000 0x64e
|
||||
.debug_info 0x00000000 0x21a build/gpio.o
|
||||
.debug_info 0x0000021a 0x2ac build/main.o
|
||||
.debug_info 0x000004c6 0x188 build/startup.o
|
||||
.debug_info 0x00000000 0xf1e
|
||||
.debug_info 0x00000000 0x262 build/gpio.o
|
||||
.debug_info 0x00000262 0x47e build/main.o
|
||||
.debug_info 0x000006e0 0x188 build/startup.o
|
||||
.debug_info 0x00000868 0x335 build/timer.o
|
||||
.debug_info 0x00000b9d 0x381 build/usart.o
|
||||
|
||||
.debug_abbrev 0x00000000 0x36d
|
||||
.debug_abbrev 0x00000000 0x12b build/gpio.o
|
||||
.debug_abbrev 0x0000012b 0x11b build/main.o
|
||||
.debug_abbrev 0x00000246 0x127 build/startup.o
|
||||
.debug_abbrev 0x00000000 0x5ae
|
||||
.debug_abbrev 0x00000000 0x11d build/gpio.o
|
||||
.debug_abbrev 0x0000011d 0x14b build/main.o
|
||||
.debug_abbrev 0x00000268 0x127 build/startup.o
|
||||
.debug_abbrev 0x0000038f 0xb5 build/timer.o
|
||||
.debug_abbrev 0x00000444 0x16a build/usart.o
|
||||
|
||||
.debug_aranges 0x00000000 0x80
|
||||
.debug_aranges 0x00000000 0xe8
|
||||
.debug_aranges
|
||||
0x00000000 0x28 build/gpio.o
|
||||
0x00000000 0x30 build/gpio.o
|
||||
.debug_aranges
|
||||
0x00000028 0x28 build/main.o
|
||||
0x00000030 0x28 build/main.o
|
||||
.debug_aranges
|
||||
0x00000050 0x30 build/startup.o
|
||||
0x00000058 0x30 build/startup.o
|
||||
.debug_aranges
|
||||
0x00000088 0x28 build/timer.o
|
||||
.debug_aranges
|
||||
0x000000b0 0x38 build/usart.o
|
||||
|
||||
.debug_rnglists
|
||||
0x00000000 0x51
|
||||
0x00000000 0x99
|
||||
.debug_rnglists
|
||||
0x00000000 0x19 build/gpio.o
|
||||
0x00000000 0x20 build/gpio.o
|
||||
.debug_rnglists
|
||||
0x00000019 0x19 build/main.o
|
||||
0x00000020 0x1b build/main.o
|
||||
.debug_rnglists
|
||||
0x00000032 0x1f build/startup.o
|
||||
0x0000003b 0x1f build/startup.o
|
||||
.debug_rnglists
|
||||
0x0000005a 0x19 build/timer.o
|
||||
.debug_rnglists
|
||||
0x00000073 0x26 build/usart.o
|
||||
|
||||
.debug_macro 0x00000000 0x2d8f
|
||||
.debug_macro 0x00000000 0x4853
|
||||
.debug_macro 0x00000000 0xb56 build/gpio.o
|
||||
.debug_macro 0x00000b56 0x22 build/gpio.o
|
||||
.debug_macro 0x00000b78 0x75 build/gpio.o
|
||||
@@ -260,32 +369,47 @@ LOAD linker stubs
|
||||
.debug_macro 0x0000108c 0x89 build/gpio.o
|
||||
.debug_macro 0x00001115 0x4cc build/gpio.o
|
||||
.debug_macro 0x000015e1 0x22 build/gpio.o
|
||||
.debug_macro 0x00001603 0x34 build/gpio.o
|
||||
.debug_macro 0x00001637 0xb6b build/main.o
|
||||
.debug_macro 0x000021a2 0x16 build/main.o
|
||||
.debug_macro 0x000021b8 0x2e build/main.o
|
||||
.debug_macro 0x000021e6 0xb02 build/startup.o
|
||||
.debug_macro 0x00002ce8 0x56 build/startup.o
|
||||
.debug_macro 0x00002d3e 0x51 build/startup.o
|
||||
.debug_macro 0x00001603 0x46 build/gpio.o
|
||||
.debug_macro 0x00001649 0xb89 build/main.o
|
||||
.debug_macro 0x000021d2 0x16d build/main.o
|
||||
.debug_macro 0x0000233f 0x46 build/main.o
|
||||
.debug_macro 0x00002385 0x2e build/main.o
|
||||
.debug_macro 0x000023b3 0x22 build/main.o
|
||||
.debug_macro 0x000023d5 0x5e build/main.o
|
||||
.debug_macro 0x00002433 0xb02 build/startup.o
|
||||
.debug_macro 0x00002f35 0x56 build/startup.o
|
||||
.debug_macro 0x00002f8b 0x51 build/startup.o
|
||||
.debug_macro 0x00002fdc 0xb5c build/timer.o
|
||||
.debug_macro 0x00003b38 0x167 build/timer.o
|
||||
.debug_macro 0x00003c9f 0xb74 build/usart.o
|
||||
.debug_macro 0x00004813 0x40 build/usart.o
|
||||
|
||||
.debug_line 0x00000000 0x2fe
|
||||
.debug_line 0x00000000 0x116 build/gpio.o
|
||||
.debug_line 0x00000116 0xfe build/main.o
|
||||
.debug_line 0x00000214 0xea build/startup.o
|
||||
.debug_line 0x00000000 0x691
|
||||
.debug_line 0x00000000 0x179 build/gpio.o
|
||||
.debug_line 0x00000179 0x1d2 build/main.o
|
||||
.debug_line 0x0000034b 0xea build/startup.o
|
||||
.debug_line 0x00000435 0xdf build/timer.o
|
||||
.debug_line 0x00000514 0x17d build/usart.o
|
||||
|
||||
.debug_str 0x00000000 0x553c
|
||||
.debug_str 0x00000000 0x5372 build/gpio.o
|
||||
0x551a (size before relaxing)
|
||||
.debug_str 0x00005372 0x142 build/main.o
|
||||
0x5607 (size before relaxing)
|
||||
.debug_str 0x000054b4 0x88 build/startup.o
|
||||
0x3cdf (size before relaxing)
|
||||
.debug_str 0x00000000 0x626f
|
||||
.debug_str 0x00000000 0x53d8 build/gpio.o
|
||||
0x5588 (size before relaxing)
|
||||
.debug_str 0x000053d8 0xdce build/main.o
|
||||
0x62e8 (size before relaxing)
|
||||
.debug_str 0x000061a6 0x88 build/startup.o
|
||||
0x3cdc (size before relaxing)
|
||||
.debug_str 0x0000622e 0xc build/timer.o
|
||||
0x5c41 (size before relaxing)
|
||||
.debug_str 0x0000623a 0x35 build/usart.o
|
||||
0x5fac (size before relaxing)
|
||||
|
||||
.comment 0x00000000 0x45
|
||||
.comment 0x00000000 0x45 build/gpio.o
|
||||
0x46 (size before relaxing)
|
||||
.comment 0x00000045 0x46 build/main.o
|
||||
.comment 0x00000045 0x46 build/startup.o
|
||||
.comment 0x00000045 0x46 build/timer.o
|
||||
.comment 0x00000045 0x46 build/usart.o
|
||||
|
||||
.ARM.attributes
|
||||
0x00000000 0x34
|
||||
@@ -295,20 +419,32 @@ LOAD linker stubs
|
||||
0x00000034 0x34 build/main.o
|
||||
.ARM.attributes
|
||||
0x00000068 0x34 build/startup.o
|
||||
.ARM.attributes
|
||||
0x0000009c 0x34 build/timer.o
|
||||
.ARM.attributes
|
||||
0x000000d0 0x34 build/usart.o
|
||||
|
||||
.debug_line_str
|
||||
0x00000000 0x265
|
||||
0x00000000 0x290
|
||||
.debug_line_str
|
||||
0x00000000 0x24e build/gpio.o
|
||||
0x260 (size before relaxing)
|
||||
0x00000000 0x24b build/gpio.o
|
||||
0x25d (size before relaxing)
|
||||
.debug_line_str
|
||||
0x0000024e 0xd build/main.o
|
||||
0x266 (size before relaxing)
|
||||
0x0000024b 0x2b build/main.o
|
||||
0x281 (size before relaxing)
|
||||
.debug_line_str
|
||||
0x0000025b 0xa build/startup.o
|
||||
0x21b (size before relaxing)
|
||||
0x00000276 0xa build/startup.o
|
||||
0x218 (size before relaxing)
|
||||
.debug_line_str
|
||||
0x00000280 0x8 build/timer.o
|
||||
0x25b (size before relaxing)
|
||||
.debug_line_str
|
||||
0x00000288 0x8 build/usart.o
|
||||
0x26c (size before relaxing)
|
||||
|
||||
.debug_frame 0x00000000 0x124
|
||||
.debug_frame 0x00000000 0x60 build/gpio.o
|
||||
.debug_frame 0x00000060 0x58 build/main.o
|
||||
.debug_frame 0x000000b8 0x6c build/startup.o
|
||||
.debug_frame 0x00000000 0x234
|
||||
.debug_frame 0x00000000 0x88 build/gpio.o
|
||||
.debug_frame 0x00000088 0x50 build/main.o
|
||||
.debug_frame 0x000000d8 0x6c build/startup.o
|
||||
.debug_frame 0x00000144 0x50 build/timer.o
|
||||
.debug_frame 0x00000194 0xa0 build/usart.o
|
||||
|
||||
+509
-336
File diff suppressed because it is too large
Load Diff
+30
-11
@@ -1,5 +1,5 @@
|
||||
# 0 "src/gpio.c"
|
||||
# 1 "/home/alex/code/own/c-compile-experiments//"
|
||||
# 1 "/home/alex/code/own/stm32-falling-sand//"
|
||||
# 0 "<built-in>"
|
||||
#define __STDC__ 1
|
||||
# 0 "<built-in>"
|
||||
@@ -1995,17 +1995,23 @@ struct gpio {
|
||||
volatile uint32_t ODR;
|
||||
volatile uint32_t BSRR;
|
||||
volatile uint32_t LCKR;
|
||||
volatile uint32_t AFRL[2];
|
||||
volatile uint32_t AFRH[2];
|
||||
volatile uint32_t AFRL;
|
||||
volatile uint32_t AFRH;
|
||||
};
|
||||
|
||||
|
||||
#define GPIO_AF_MCO_1 (0b0000)
|
||||
#define GPIO_AF_USART2_RX (0b0111)
|
||||
#define GPIO_AF_USART2_TX (0b0111)
|
||||
|
||||
#define GPIO_BASE_ADDR (0x40020000U)
|
||||
#define GPIO_PORT_OFFSET (0x400U)
|
||||
#define GPIO(port) ((struct gpio*)(uintptr_t)(GPIO_BASE_ADDR + (GPIO_PORT_OFFSET * port)))
|
||||
|
||||
#define BIT(x) (1 << x)
|
||||
|
||||
#define PIN(port,num) ((((port) - 'A') << 8) | num)
|
||||
#define PORT(port) (((port) - 'A') << 8)
|
||||
|
||||
#define PIN(port,num) (PORT(port) | num)
|
||||
|
||||
#define PINNUM(pin) (pin & 0b1111)
|
||||
|
||||
@@ -2019,24 +2025,37 @@ typedef enum {
|
||||
} GPIO_MODE;
|
||||
|
||||
void gpio_set_mode(uint16_t pin, GPIO_MODE mode);
|
||||
void gpio_set_af(uint16_t pin, uint8_t af);
|
||||
void gpio_write(uint16_t pin,
|
||||
# 40 "src/gpio.h" 3 4
|
||||
# 47 "src/gpio.h" 3 4
|
||||
_Bool
|
||||
# 40 "src/gpio.h"
|
||||
# 47 "src/gpio.h"
|
||||
val);
|
||||
# 5 "src/gpio.c" 2
|
||||
|
||||
void gpio_set_mode(uint16_t pin, GPIO_MODE mode) {
|
||||
struct gpio *gpio = ((struct gpio*)(uintptr_t)((0x40020000U) + ((0x400U) * (pin >> 8))));
|
||||
int pn = (pin & 0b1111);
|
||||
gpio->MODER &= ~(0x0011 << (pn * 2));
|
||||
gpio->MODER |= (mode & 0b011) << (pn * 2);
|
||||
gpio->MODER &= ~(0b11 << (pn * 2));
|
||||
gpio->MODER |= (mode & 0b11) << (pn * 2);
|
||||
}
|
||||
|
||||
void gpio_set_af(uint16_t pin, uint8_t af) {
|
||||
struct gpio *gpio = ((struct gpio*)(uintptr_t)((0x40020000U) + ((0x400U) * (pin >> 8))));
|
||||
int pn = (pin & 0b1111);
|
||||
if (pn < 8) {
|
||||
gpio->AFRL &= ~(0b1111 << (pn * 4));
|
||||
gpio->AFRL |= (af & 0b1111) << (pn * 4);
|
||||
} else {
|
||||
gpio->AFRH &= ~(0b1111 << (pn * 4));
|
||||
gpio->AFRH |= (af & 0b1111) << (pn * 4);
|
||||
}
|
||||
}
|
||||
|
||||
void gpio_write(uint16_t pin,
|
||||
# 13 "src/gpio.c" 3 4
|
||||
# 25 "src/gpio.c" 3 4
|
||||
_Bool
|
||||
# 13 "src/gpio.c"
|
||||
# 25 "src/gpio.c"
|
||||
val) {
|
||||
struct gpio *gpio = ((struct gpio*)(uintptr_t)((0x40020000U) + ((0x400U) * (pin >> 8))));
|
||||
gpio->BSRR = (0b0011 << (pin & 0b1111)) << (val ? 0 : 16);
|
||||
|
||||
Binary file not shown.
+1558
-476
File diff suppressed because it is too large
Load Diff
+362
-35
@@ -1,5 +1,5 @@
|
||||
# 0 "src/main.c"
|
||||
# 1 "/home/alex/code/own/c-compile-experiments//"
|
||||
# 1 "/home/alex/code/own/stm32-falling-sand//"
|
||||
# 0 "<built-in>"
|
||||
#define __STDC__ 1
|
||||
# 0 "<built-in>"
|
||||
@@ -1963,6 +1963,20 @@ extern intmax_t _wcstoimax_r(struct _reent *, const wchar_t *__restrict, wchar_t
|
||||
extern uintmax_t wcstoumax(const wchar_t *__restrict, wchar_t **__restrict, int);
|
||||
extern uintmax_t _wcstoumax_r(struct _reent *, const wchar_t *__restrict, wchar_t **__restrict, int);
|
||||
# 2 "src/main.c" 2
|
||||
# 1 "/nix/store/yr89i11mszv2az19r26l372zgaiivj1c-gcc-arm-embedded-12.3.rel1/lib/gcc/arm-none-eabi/12.3.1/include/stdbool.h" 1 3 4
|
||||
# 29 "/nix/store/yr89i11mszv2az19r26l372zgaiivj1c-gcc-arm-embedded-12.3.rel1/lib/gcc/arm-none-eabi/12.3.1/include/stdbool.h" 3 4
|
||||
#define _STDBOOL_H
|
||||
|
||||
|
||||
|
||||
#define bool _Bool
|
||||
|
||||
#define true ((_Bool)+1u)
|
||||
#define false ((_Bool)+0u)
|
||||
# 50 "/nix/store/yr89i11mszv2az19r26l372zgaiivj1c-gcc-arm-embedded-12.3.rel1/lib/gcc/arm-none-eabi/12.3.1/include/stdbool.h" 3 4
|
||||
#define __bool_true_false_are_defined 1
|
||||
# 3 "src/main.c" 2
|
||||
|
||||
# 1 "src/rcc.h" 1
|
||||
|
||||
#define RCC_H_
|
||||
@@ -2004,26 +2018,114 @@ struct rcc {
|
||||
|
||||
#define RCC_BASE_ADDR (0x40023800U)
|
||||
#define RCC ((struct rcc *) RCC_BASE_ADDR)
|
||||
# 3 "src/main.c" 2
|
||||
|
||||
|
||||
|
||||
#define RCC_CR_PLLRDY_BIT 25
|
||||
#define RCC_CR_PLLRDY_LOCKED (1 << RCC_CR_PLLRDY_BIT)
|
||||
|
||||
|
||||
#define RCC_CR_PLLON_BIT 24
|
||||
#define RCC_CR_PLLON_ON (1 << RCC_CR_PLLON_BIT)
|
||||
|
||||
|
||||
#define RCC_CR_HSERDY_BIT 17
|
||||
#define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT)
|
||||
|
||||
|
||||
#define RCC_CR_HSEON_BIT 16
|
||||
#define RCC_CR_HSEON_ON (1 << RCC_CR_HSEON_BIT)
|
||||
|
||||
|
||||
#define RCC_CR_HSIRDY_BIT 1
|
||||
#define RCC_CR_HSIRDY_READY (1 << RCC_CR_HSIRDY_BIT)
|
||||
|
||||
|
||||
#define RCC_CR_HSION_BIT 0
|
||||
#define RCC_CR_HSION_ON (1 << RCC_CR_HSION_BIT)
|
||||
|
||||
|
||||
#define RCC_PLLCFGR_PLLQ_BIT 24
|
||||
#define RCC_PLLCFGR_PLLQ_MASK (0b1111)
|
||||
#define RCC_PLLCFGR_PLLQ(q) ((q & RCC_PLLCFGR_PLLQ_MASK) << RCC_PLLCFGR_PLLQ_BIT)
|
||||
|
||||
#define RCC_PLLCFGR_PLLSRC_BIT 22
|
||||
#define RCC_PLLCFGR_PLLSRC_HSE (1 << RCC_PLLCFGR_PLLSRC_BIT)
|
||||
|
||||
#define RCC_PLLCFGR_PLLP_BIT 16
|
||||
#define RCC_PLLCFGR_PLLP_MASK (0b11)
|
||||
#define RCC_PLLCFGR_PLLP(p) ((p & RCC_PLLCFGR_PLLP_MASK) << RCC_PLLCFGR_PLLP_BIT)
|
||||
|
||||
#define RCC_PLLCFGR_PLLN_BIT 6
|
||||
#define RCC_PLLCFGR_PLLN_MASK (0b111111111)
|
||||
#define RCC_PLLCFGR_PLLN(n) ((n & RCC_PLLCFGR_PLLN_MASK) << RCC_PLLCFGR_PLLN_BIT)
|
||||
|
||||
#define RCC_PLLCFGR_PLLM_BIT 0
|
||||
#define RCC_PLLCFGR_PLLM_MASK (0b111111)
|
||||
#define RCC_PLLCFGR_PLLM(m) ((m & RCC_PLLCFGR_PLLM_MASK) << RCC_PLLCFGR_PLLM_BIT)
|
||||
|
||||
|
||||
|
||||
#define RCC_CFGR_PPRE_DIV_NONE 0
|
||||
#define RCC_CFGR_PPRE_DIV_2 (0b100)
|
||||
|
||||
|
||||
#define RCC_CFGR_MCO1_HSE (0b10)
|
||||
#define RCC_CFGR_MCO1_PLL (0b11)
|
||||
|
||||
#define RCC_CFGR_MCO1_BIT 21
|
||||
#define RCC_CFGR_MCO1_MASK (0b11)
|
||||
|
||||
#define RCC_CFGR_MCO1PRE_DIV4 (0b110)
|
||||
#define RCC_CFGR_MCO1PRE_DIV2 (0b100)
|
||||
|
||||
#define RCC_CFGR_MCO1PRE_BIT 24
|
||||
#define RCC_CFGR_MCO1PRE_MASK (0b111)
|
||||
|
||||
|
||||
#define RCC_CFGR_PPRE2_BIT 13
|
||||
#define RCC_CFGR_PPRE2_MASK (0b111)
|
||||
|
||||
|
||||
#define RCC_CFGR_PPRE1_BIT 10
|
||||
#define RCC_CFGR_PPRE1_MASK (0b111)
|
||||
|
||||
|
||||
#define RCC_CFGR_HPRE_DIV_NONE 0
|
||||
|
||||
#define RCC_CFGR_HPRE_BIT 4
|
||||
#define RCC_CFGR_HPRE_MASK (0b1111)
|
||||
|
||||
|
||||
#define RCC_CFGR_SWS_PLL (0b10)
|
||||
|
||||
#define RCC_CFGR_SWS_BIT 2
|
||||
#define RCC_CFGR_SWS_MASK (0b11)
|
||||
|
||||
|
||||
#define RCC_CFGR_SW_PLL (0b10)
|
||||
|
||||
#define RCC_CFGR_SW_BIT 0
|
||||
#define RCC_CFGR_SW_MASK (0b11)
|
||||
#define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT)
|
||||
|
||||
|
||||
#define RCC_APB1ENR_PWREN_BIT 28
|
||||
#define RCC_APB1ENR_PWREN_CLOCK_ENABLE (1 << RCC_APB1ENR_PWREN_BIT)
|
||||
|
||||
#define RCC_APB1ENR_USART2EN_BIT 17
|
||||
#define RCC_APB1ENR_USART2EN_ENABLE (1 << RCC_APB1ENR_USART2EN_BIT)
|
||||
|
||||
#define RCC_APB1ENR_TIM4_BIT 2
|
||||
#define RCC_APB1ENR_TIM4_ENABLE (1 << RCC_APB1ENR_TIM4_BIT)
|
||||
# 5 "src/main.c" 2
|
||||
# 1 "src/gpio.h" 1
|
||||
|
||||
#define GPIO_H_
|
||||
|
||||
# 1 "/nix/store/yr89i11mszv2az19r26l372zgaiivj1c-gcc-arm-embedded-12.3.rel1/lib/gcc/arm-none-eabi/12.3.1/include/stdbool.h" 1 3 4
|
||||
# 29 "/nix/store/yr89i11mszv2az19r26l372zgaiivj1c-gcc-arm-embedded-12.3.rel1/lib/gcc/arm-none-eabi/12.3.1/include/stdbool.h" 3 4
|
||||
#define _STDBOOL_H
|
||||
|
||||
|
||||
|
||||
#define bool _Bool
|
||||
|
||||
#define true ((_Bool)+1u)
|
||||
#define false ((_Bool)+0u)
|
||||
# 50 "/nix/store/yr89i11mszv2az19r26l372zgaiivj1c-gcc-arm-embedded-12.3.rel1/lib/gcc/arm-none-eabi/12.3.1/include/stdbool.h" 3 4
|
||||
#define __bool_true_false_are_defined 1
|
||||
# 5 "src/gpio.h" 2
|
||||
|
||||
|
||||
struct gpio {
|
||||
volatile uint32_t MODER;
|
||||
volatile uint32_t OTYPER;
|
||||
@@ -2033,17 +2135,23 @@ struct gpio {
|
||||
volatile uint32_t ODR;
|
||||
volatile uint32_t BSRR;
|
||||
volatile uint32_t LCKR;
|
||||
volatile uint32_t AFRL[2];
|
||||
volatile uint32_t AFRH[2];
|
||||
volatile uint32_t AFRL;
|
||||
volatile uint32_t AFRH;
|
||||
};
|
||||
|
||||
|
||||
#define GPIO_AF_MCO_1 (0b0000)
|
||||
#define GPIO_AF_USART2_RX (0b0111)
|
||||
#define GPIO_AF_USART2_TX (0b0111)
|
||||
|
||||
#define GPIO_BASE_ADDR (0x40020000U)
|
||||
#define GPIO_PORT_OFFSET (0x400U)
|
||||
#define GPIO(port) ((struct gpio*)(uintptr_t)(GPIO_BASE_ADDR + (GPIO_PORT_OFFSET * port)))
|
||||
|
||||
#define BIT(x) (1 << x)
|
||||
|
||||
#define PIN(port,num) ((((port) - 'A') << 8) | num)
|
||||
#define PORT(port) (((port) - 'A') << 8)
|
||||
|
||||
#define PIN(port,num) (PORT(port) | num)
|
||||
|
||||
#define PINNUM(pin) (pin & 0b1111)
|
||||
|
||||
@@ -2057,36 +2165,255 @@ typedef enum {
|
||||
} GPIO_MODE;
|
||||
|
||||
void gpio_set_mode(uint16_t pin, GPIO_MODE mode);
|
||||
void gpio_set_af(uint16_t pin, uint8_t af);
|
||||
void gpio_write(uint16_t pin,
|
||||
# 40 "src/gpio.h" 3 4
|
||||
# 47 "src/gpio.h" 3 4
|
||||
_Bool
|
||||
# 40 "src/gpio.h"
|
||||
# 47 "src/gpio.h"
|
||||
val);
|
||||
# 4 "src/main.c" 2
|
||||
# 6 "src/main.c" 2
|
||||
# 1 "src/flash.h" 1
|
||||
|
||||
#define FLASH_H_
|
||||
|
||||
|
||||
|
||||
struct flash {
|
||||
volatile uint32_t ACR;
|
||||
volatile uint32_t KEYR;
|
||||
volatile uint32_t OPTKEYR;
|
||||
volatile uint32_t SR;
|
||||
volatile uint32_t CR;
|
||||
volatile uint32_t OPTCR;
|
||||
};
|
||||
|
||||
#define FLASH_BASE_ADDR (0x40023C00U)
|
||||
#define FLASH ((struct flash *) FLASH_BASE_ADDR)
|
||||
|
||||
|
||||
|
||||
#define FLASH_ACR_DCEN_BIT 10
|
||||
#define FLASH_ACR_DCEN_ENABLE (1 <<FLASH_ACR_DCEN_BIT)
|
||||
|
||||
|
||||
#define FLASH_ACR_ICEN_BIT 9
|
||||
#define FLASH_ACR_ICEN_ENABLE (1 <<FLASH_ACR_ICEN_BIT)
|
||||
|
||||
|
||||
#define FLASH_ACR_LATENCY_3_WAIT_STATES (0b0011)
|
||||
|
||||
#define FLASH_ACR_LATENCY_BIT 0
|
||||
#define FLASH_ACR_LATENCY_MASK (0b1111)
|
||||
#define FLASH_ACR_LATENCY(latency) ((latency & FLASH_ACR_LATENCY_MASK) << FLASH_ACR_LATENCY_BIT)
|
||||
# 7 "src/main.c" 2
|
||||
# 1 "src/pwr.h" 1
|
||||
|
||||
#define PWR_H_
|
||||
|
||||
|
||||
|
||||
struct pwr {
|
||||
volatile uint32_t CR;
|
||||
volatile uint32_t CSR;
|
||||
};
|
||||
|
||||
#define PWR_BASE_ADDR (0x40007000U)
|
||||
#define PWR ((struct pwr *) PWR_BASE_ADDR)
|
||||
|
||||
|
||||
#define PWR_SCALE3 (0b11)
|
||||
|
||||
|
||||
#define PWR_CR_VOS_BIT 14
|
||||
#define PWR_CR_VOS_MASK (0b11)
|
||||
#define PWR_CR_VOS(scale) ((scale & PWR_CR_VOS_MASK) << PWR_CR_VOS_BIT)
|
||||
# 8 "src/main.c" 2
|
||||
# 1 "src/timer.h" 1
|
||||
|
||||
#define TIMER_H_
|
||||
|
||||
|
||||
|
||||
struct timer {
|
||||
volatile uint32_t CR1;
|
||||
volatile uint32_t CR2;
|
||||
volatile uint32_t SMCR;
|
||||
volatile uint32_t DIER;
|
||||
volatile uint32_t SR;
|
||||
volatile uint32_t EGR;
|
||||
volatile uint32_t CCMR1;
|
||||
volatile uint32_t CCMR2;
|
||||
volatile uint32_t CCER;
|
||||
volatile uint32_t CNT;
|
||||
volatile uint32_t PSC;
|
||||
volatile uint32_t ARR;
|
||||
volatile uint32_t RCR;
|
||||
volatile uint32_t CCR1;
|
||||
volatile uint32_t CCR2;
|
||||
volatile uint32_t CCR3;
|
||||
volatile uint32_t CCR4;
|
||||
volatile uint32_t BDTR;
|
||||
volatile uint32_t DCR;
|
||||
volatile uint32_t DMAR;
|
||||
};
|
||||
|
||||
#define TIM4_BASE_ADDR (0x40000800U)
|
||||
#define TIM4 ((struct timer *) TIM4_BASE_ADDR)
|
||||
|
||||
#define TIM_CR1_CEN_BIT 0
|
||||
#define TIM_ENABLE (1 << TIM_CR1_CEN_BIT)
|
||||
|
||||
void tim4_init(void);
|
||||
void tim4_start(void);
|
||||
# 9 "src/main.c" 2
|
||||
# 1 "src/usart.h" 1
|
||||
|
||||
#define USART_H_
|
||||
|
||||
|
||||
|
||||
struct usart {
|
||||
volatile uint32_t SR;
|
||||
volatile uint32_t DR;
|
||||
volatile uint32_t BRR;
|
||||
volatile uint32_t CR1;
|
||||
volatile uint32_t CR2;
|
||||
volatile uint32_t CR3;
|
||||
volatile uint32_t GTPR;
|
||||
};
|
||||
|
||||
#define USART2_BASE_ADDR (0x40004400U)
|
||||
#define USART2 ((struct usart *) USART2_BASE_ADDR)
|
||||
|
||||
|
||||
|
||||
#define USART_SR_TC_BIT 6
|
||||
#define USART_SR_TC_COMPLETED (1 << USART_SR_TC_BIT)
|
||||
|
||||
|
||||
|
||||
#define USART_CR1_UE_BIT 13
|
||||
#define USART_CR1_UE_ENABLE (1 << USART_CR1_UE_BIT)
|
||||
|
||||
|
||||
#define USART_CR1_TE_BIT 3
|
||||
#define USART_CR1_TE_ENABLE (1 << USART_CR1_TE_BIT)
|
||||
|
||||
|
||||
#define USART_CR1_RE_BIT 2
|
||||
#define USART_CR1_RE_ENABLE (1 << USART_CR1_RE_BIT)
|
||||
|
||||
|
||||
#define USART_BRR_MANTISSA_BIT 4
|
||||
#define USART_BRR_MANTISSA_MASK (0b111111111111)
|
||||
|
||||
#define USART_BRR_FRACTION_BIT 0
|
||||
#define USART_BRR_FRACTION_MASK (0b111)
|
||||
|
||||
void usart2_init(void);
|
||||
void usart2_start(void);
|
||||
|
||||
void usart2_write_byte(uint8_t byte);
|
||||
void usart2_write(char *buf);
|
||||
# 10 "src/main.c" 2
|
||||
|
||||
#define exit 42
|
||||
|
||||
static inline void spin(volatile uint32_t count) {
|
||||
while (count--) (void) 0;
|
||||
static void system_clock_init(void) {
|
||||
|
||||
((struct rcc *) (0x40023800U))->APB1ENR |= (1 << 28);
|
||||
|
||||
|
||||
((struct pwr *) (0x40007000U))->CR &= ~((0b11) << 14);
|
||||
((struct pwr *) (0x40007000U))->CR |= ((0b11) << 14);
|
||||
|
||||
|
||||
((struct rcc *) (0x40023800U))->CR &= ~(1 << 0);
|
||||
|
||||
|
||||
((struct rcc *) (0x40023800U))->CR |= (1 << 16);
|
||||
|
||||
|
||||
|
||||
while (!(((struct rcc *) (0x40023800U))->CR & (1 << 17)));
|
||||
|
||||
|
||||
|
||||
((struct rcc *) (0x40023800U))->CR &= ~(1 << 24);
|
||||
|
||||
|
||||
((struct rcc *) (0x40023800U))->PLLCFGR |= (1 << 22);
|
||||
|
||||
|
||||
((struct rcc *) (0x40023800U))->PLLCFGR |= ((25 & (0b111111)) << 0) | ((192 & (0b111111111)) << 6) | ((2 & (0b11)) << 16) | ((4 & (0b1111)) << 24);
|
||||
|
||||
|
||||
((struct rcc *) (0x40023800U))->CFGR &= ~((0b1111) << 4);
|
||||
((struct rcc *) (0x40023800U))->CFGR |= (0 << 4);
|
||||
|
||||
|
||||
((struct rcc *) (0x40023800U))->CFGR &= ~((0b111) << 10);
|
||||
((struct rcc *) (0x40023800U))->CFGR |= ((0b100) << 10);
|
||||
|
||||
|
||||
((struct rcc *) (0x40023800U))->CFGR &= ~((0b111) << 13);
|
||||
((struct rcc *) (0x40023800U))->CFGR |= (0 << 13);
|
||||
|
||||
|
||||
((struct rcc *) (0x40023800U))->CR |= (1 << 24);
|
||||
|
||||
|
||||
|
||||
while (!(((struct rcc *) (0x40023800U))->CR & (1 << 25)));
|
||||
|
||||
|
||||
((struct flash *) (0x40023C00U))->ACR |= (1 <<10);
|
||||
((struct flash *) (0x40023C00U))->ACR |= (1 <<9);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
((struct rcc *) (0x40023800U))->CFGR |= (((0b10) & (0b11)) << 0);
|
||||
|
||||
|
||||
|
||||
while (((((struct rcc *) (0x40023800U))->CFGR >> 2) & (0b11)) != (0b10));
|
||||
}
|
||||
|
||||
int main(void) {
|
||||
(void) system_clock_init();
|
||||
(void) tim4_init();
|
||||
(void) usart2_init();
|
||||
|
||||
(void) tim4_start();
|
||||
(void) usart2_start();
|
||||
|
||||
uint16_t led = (((('C') - 'A') << 8) | 13);
|
||||
((struct rcc *) (0x40023800U))->AHB1ENR |= (1 << (led >> 8));
|
||||
gpio_set_mode(led, GPIO_MODE_OUTPUT);
|
||||
for (;;) {
|
||||
gpio_write(led,
|
||||
# 16 "src/main.c" 3 4
|
||||
((_Bool)+1u)
|
||||
# 16 "src/main.c"
|
||||
);
|
||||
spin(999999);
|
||||
gpio_write(led,
|
||||
# 18 "src/main.c" 3 4
|
||||
|
||||
uint16_t counter = ((struct timer *) (0x40000800U))->CNT;
|
||||
|
||||
# 90 "src/main.c" 3 4
|
||||
_Bool
|
||||
# 90 "src/main.c"
|
||||
led_on =
|
||||
# 90 "src/main.c" 3 4
|
||||
((_Bool)+0u)
|
||||
# 18 "src/main.c"
|
||||
);
|
||||
spin(999999);
|
||||
# 90 "src/main.c"
|
||||
;
|
||||
while(1) {
|
||||
if ((((struct timer *) (0x40000800U))->CNT - counter) >= 250) {
|
||||
led_on = !led_on;
|
||||
gpio_write(led, led_on);
|
||||
|
||||
usart2_write("hello, world!\n");
|
||||
|
||||
counter = ((struct timer *) (0x40000800U))->CNT;
|
||||
}
|
||||
};
|
||||
|
||||
return 42;
|
||||
|
||||
Binary file not shown.
+16
-16
@@ -2923,6 +2923,8 @@ interrupt_vector_table:
|
||||
.ascii "INOR__ >= ((maj) << 16) + (min))\000"
|
||||
.LASF171:
|
||||
.ascii "__DBL_MAX__ ((double)1.7976931348623157e+308L)\000"
|
||||
.LASF602:
|
||||
.ascii "UINTMAX_C(x) __UINTMAX_C(x)\000"
|
||||
.LASF253:
|
||||
.ascii "__USFRACT_MIN__ 0.0UHR\000"
|
||||
.LASF578:
|
||||
@@ -3020,8 +3022,8 @@ interrupt_vector_table:
|
||||
.ascii "__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__\000"
|
||||
.LASF200:
|
||||
.ascii "__FLT32_MIN_10_EXP__ (-37)\000"
|
||||
.LASF176:
|
||||
.ascii "__DBL_HAS_DENORM__ 1\000"
|
||||
.LASF492:
|
||||
.ascii "__int20\000"
|
||||
.LASF267:
|
||||
.ascii "__LFRACT_IBIT__ 0\000"
|
||||
.LASF497:
|
||||
@@ -3106,8 +3108,8 @@ interrupt_vector_table:
|
||||
.ascii "__ARM_NEON\000"
|
||||
.LASF401:
|
||||
.ascii "__ARM_FEATURE_CMSE\000"
|
||||
.LASF625:
|
||||
.ascii "/home/alex/code/own/c-compile-experiments\000"
|
||||
.LASF68:
|
||||
.ascii "__UINTPTR_TYPE__ unsigned int\000"
|
||||
.LASF229:
|
||||
.ascii "__FLT64_IS_IEC_60559__ 2\000"
|
||||
.LASF209:
|
||||
@@ -3473,8 +3475,6 @@ interrupt_vector_table:
|
||||
.ascii "UINT16_C(x) __UINT16_C(x)\000"
|
||||
.LASF344:
|
||||
.ascii "__UTQ_FBIT__ 128\000"
|
||||
.LASF499:
|
||||
.ascii "__int20 +2\000"
|
||||
.LASF610:
|
||||
.ascii "long long int\000"
|
||||
.LASF24:
|
||||
@@ -3539,8 +3539,8 @@ interrupt_vector_table:
|
||||
.ascii "__STDC__ 1\000"
|
||||
.LASF17:
|
||||
.ascii "__SIZEOF_LONG__ 4\000"
|
||||
.LASF492:
|
||||
.ascii "__int20\000"
|
||||
.LASF499:
|
||||
.ascii "__int20 +2\000"
|
||||
.LASF168:
|
||||
.ascii "__DBL_MAX_EXP__ 1024\000"
|
||||
.LASF585:
|
||||
@@ -3567,6 +3567,8 @@ interrupt_vector_table:
|
||||
.ascii "__SCHAR_WIDTH__ 8\000"
|
||||
.LASF298:
|
||||
.ascii "__ACCUM_MIN__ (-0X1P15K-0X1P15K)\000"
|
||||
.LASF40:
|
||||
.ascii "__CHAR16_TYPE__ short unsigned int\000"
|
||||
.LASF21:
|
||||
.ascii "__SIZEOF_DOUBLE__ 8\000"
|
||||
.LASF7:
|
||||
@@ -3801,8 +3803,8 @@ interrupt_vector_table:
|
||||
.ascii "SIZE_MAX (__SIZE_MAX__)\000"
|
||||
.LASF54:
|
||||
.ascii "__INT_LEAST64_TYPE__ long long int\000"
|
||||
.LASF602:
|
||||
.ascii "UINTMAX_C(x) __UINTMAX_C(x)\000"
|
||||
.LASF128:
|
||||
.ascii "__INT_FAST16_MAX__ 0x7fffffff\000"
|
||||
.LASF49:
|
||||
.ascii "__UINT32_TYPE__ long unsigned int\000"
|
||||
.LASF183:
|
||||
@@ -3879,8 +3881,8 @@ interrupt_vector_table:
|
||||
.ascii "INT64_MAX (__INT64_MAX__)\000"
|
||||
.LASF518:
|
||||
.ascii "_INT8_T_DECLARED \000"
|
||||
.LASF40:
|
||||
.ascii "__CHAR16_TYPE__ short unsigned int\000"
|
||||
.LASF625:
|
||||
.ascii "/home/alex/code/own/stm32-falling-sand\000"
|
||||
.LASF370:
|
||||
.ascii "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1\000"
|
||||
.LASF151:
|
||||
@@ -4044,8 +4046,8 @@ interrupt_vector_table:
|
||||
.ascii "__FLT32X_MAX_10_EXP__ 308\000"
|
||||
.LASF140:
|
||||
.ascii "__UINTPTR_MAX__ 0xffffffffU\000"
|
||||
.LASF128:
|
||||
.ascii "__INT_FAST16_MAX__ 0x7fffffff\000"
|
||||
.LASF176:
|
||||
.ascii "__DBL_HAS_DENORM__ 1\000"
|
||||
.LASF32:
|
||||
.ascii "__GNUC_EXECUTION_CHARSET_NAME \"UTF-8\"\000"
|
||||
.LASF475:
|
||||
@@ -4072,8 +4074,6 @@ interrupt_vector_table:
|
||||
.ascii "long +4\000"
|
||||
.LASF534:
|
||||
.ascii "__int_least8_t_defined 1\000"
|
||||
.LASF68:
|
||||
.ascii "__UINTPTR_TYPE__ unsigned int\000"
|
||||
.LASF92:
|
||||
.ascii "__UINTMAX_MAX__ 0xffffffffffffffffULL\000"
|
||||
.LASF42:
|
||||
|
||||
+1
-1
@@ -1,5 +1,5 @@
|
||||
# 0 "src/startup.c"
|
||||
# 1 "/home/alex/code/own/c-compile-experiments//"
|
||||
# 1 "/home/alex/code/own/stm32-falling-sand//"
|
||||
# 0 "<built-in>"
|
||||
#define __STDC__ 1
|
||||
# 0 "<built-in>"
|
||||
|
||||
Binary file not shown.
+5659
File diff suppressed because it is too large
Load Diff
+2164
File diff suppressed because it is too large
Load Diff
Binary file not shown.
+6234
File diff suppressed because it is too large
Load Diff
+2266
File diff suppressed because it is too large
Load Diff
Binary file not shown.
@@ -5,7 +5,8 @@
|
||||
nixpkgs.url = "github:nixos/nixpkgs/nixos-unstable";
|
||||
};
|
||||
|
||||
outputs = { nixpkgs, ... }:
|
||||
outputs =
|
||||
{ nixpkgs, ... }:
|
||||
let
|
||||
systems = [ "x86_64-linux" ];
|
||||
in
|
||||
@@ -14,9 +15,14 @@
|
||||
nixpkgs.config.allowUnfree = true;
|
||||
};
|
||||
|
||||
devShells = nixpkgs.lib.genAttrs systems (system:
|
||||
devShells = nixpkgs.lib.genAttrs systems (
|
||||
system:
|
||||
let
|
||||
pkgs = nixpkgs.legacyPackages.${system};
|
||||
# pkgs = nixpkgs.legacyPackages.${system};
|
||||
pkgs = import nixpkgs {
|
||||
inherit system;
|
||||
config.allowUnfree = true;
|
||||
};
|
||||
in
|
||||
{
|
||||
default = pkgs.mkShell {
|
||||
@@ -24,6 +30,10 @@
|
||||
pkgs.gnumake
|
||||
pkgs.gcc-arm-embedded
|
||||
pkgs.stlink
|
||||
pkgs.gdb
|
||||
pkgs.openocd
|
||||
pkgs.gdbgui
|
||||
pkgs.stm32cubemx
|
||||
];
|
||||
};
|
||||
}
|
||||
|
||||
+34
@@ -0,0 +1,34 @@
|
||||
#ifndef FLASH_H_
|
||||
#define FLASH_H_
|
||||
|
||||
#include <inttypes.h>
|
||||
|
||||
struct flash {
|
||||
volatile uint32_t ACR; // Flash access control register
|
||||
volatile uint32_t KEYR; // Flash key register
|
||||
volatile uint32_t OPTKEYR; // Flash option key register
|
||||
volatile uint32_t SR; // Flash status register
|
||||
volatile uint32_t CR; // Flash control register
|
||||
volatile uint32_t OPTCR; // Flash option control register
|
||||
};
|
||||
|
||||
#define FLASH_BASE_ADDR (0x40023C00U)
|
||||
#define FLASH ((struct flash *) FLASH_BASE_ADDR)
|
||||
|
||||
// ACR Register
|
||||
// Data cache enable
|
||||
#define FLASH_ACR_DCEN_BIT 10
|
||||
#define FLASH_ACR_DCEN_ENABLE (1 <<FLASH_ACR_DCEN_BIT)
|
||||
|
||||
// Instruction cache enable
|
||||
#define FLASH_ACR_ICEN_BIT 9
|
||||
#define FLASH_ACR_ICEN_ENABLE (1 <<FLASH_ACR_ICEN_BIT)
|
||||
|
||||
// Latency
|
||||
#define FLASH_ACR_LATENCY_3_WAIT_STATES (0b0011)
|
||||
|
||||
#define FLASH_ACR_LATENCY_BIT 0 // Bits [3:0]
|
||||
#define FLASH_ACR_LATENCY_MASK (0b1111)
|
||||
#define FLASH_ACR_LATENCY(latency) ((latency & FLASH_ACR_LATENCY_MASK) << FLASH_ACR_LATENCY_BIT)
|
||||
|
||||
#endif
|
||||
+14
-2
@@ -6,8 +6,20 @@
|
||||
void gpio_set_mode(uint16_t pin, GPIO_MODE mode) {
|
||||
struct gpio *gpio = GPIO(PINPORT(pin)); // GPIO port address
|
||||
int pn = PINNUM(pin); // Pin number
|
||||
gpio->MODER &= ~(0x0011 << (pn * 2)); // Clear existing setting. Each pin uses 2 bits
|
||||
gpio->MODER |= (mode & 0b011) << (pn * 2); // Set new mode. Each pin uses 2 bits
|
||||
gpio->MODER &= ~(0b11 << (pn * 2)); // Clear existing setting. Each pin uses 2 bits
|
||||
gpio->MODER |= (mode & 0b11) << (pn * 2); // Set new mode. Each pin uses 2 bits
|
||||
}
|
||||
|
||||
void gpio_set_af(uint16_t pin, uint8_t af) {
|
||||
struct gpio *gpio = GPIO(PINPORT(pin));
|
||||
int pn = PINNUM(pin);
|
||||
if (pn < 8) {
|
||||
gpio->AFRL &= ~(0b1111 << (pn * 4)); // Each pin uses 4 bits
|
||||
gpio->AFRL |= (af & 0b1111) << (pn * 4);
|
||||
} else {
|
||||
gpio->AFRH &= ~(0b1111 << (pn * 4)); // Each pin uses 4 bits
|
||||
gpio->AFRH |= (af & 0b1111) << (pn * 4);
|
||||
}
|
||||
}
|
||||
|
||||
void gpio_write(uint16_t pin, bool val) {
|
||||
|
||||
+11
-4
@@ -13,17 +13,23 @@ struct gpio {
|
||||
volatile uint32_t ODR; // Port output data register
|
||||
volatile uint32_t BSRR; // Port bit set/reset register
|
||||
volatile uint32_t LCKR; // Port configuration lock register
|
||||
volatile uint32_t AFRL[2]; // Alternative function low register
|
||||
volatile uint32_t AFRH[2]; // Alternative function high register
|
||||
volatile uint32_t AFRL; // Alternative function low register
|
||||
volatile uint32_t AFRH; // Alternative function high register
|
||||
};
|
||||
|
||||
// AFRH, AFRL registers
|
||||
#define GPIO_AF_MCO_1 (0b0000) // Alternative function 0 (AF0)
|
||||
#define GPIO_AF_USART2_RX (0b0111) // Alternative function 7 (AF7)
|
||||
#define GPIO_AF_USART2_TX (0b0111) // Alternative function 7 (AF7)
|
||||
|
||||
#define GPIO_BASE_ADDR (0x40020000U)
|
||||
#define GPIO_PORT_OFFSET (0x400U)
|
||||
#define GPIO(port) ((struct gpio*)(uintptr_t)(GPIO_BASE_ADDR + (GPIO_PORT_OFFSET * port)))
|
||||
|
||||
#define BIT(x) (1 << x)
|
||||
// Create a 8bit number from a port
|
||||
#define PORT(port) (((port) - 'A') << 8)
|
||||
// Create a 16bit number from a port and pin
|
||||
#define PIN(port, num) ((((port) - 'A') << 8) | num)
|
||||
#define PIN(port, num) (PORT(port) | num)
|
||||
// get the lower byte from a PIN
|
||||
#define PINNUM(pin) (pin & 0b1111)
|
||||
// get the upper byte from a PIN
|
||||
@@ -37,6 +43,7 @@ typedef enum {
|
||||
} GPIO_MODE;
|
||||
|
||||
void gpio_set_mode(uint16_t pin, GPIO_MODE mode);
|
||||
void gpio_set_af(uint16_t pin, uint8_t af);
|
||||
void gpio_write(uint16_t pin, bool val);
|
||||
|
||||
#endif
|
||||
|
||||
+88
-8
@@ -1,22 +1,102 @@
|
||||
#include <inttypes.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "rcc.h"
|
||||
#include "gpio.h"
|
||||
#include "flash.h"
|
||||
#include "pwr.h"
|
||||
#include "timer.h"
|
||||
#include "usart.h"
|
||||
|
||||
#define exit 42
|
||||
|
||||
static inline void spin(volatile uint32_t count) {
|
||||
while (count--) (void) 0;
|
||||
static void system_clock_init(void) {
|
||||
// Power on clock for PLL
|
||||
RCC->APB1ENR |= RCC_APB1ENR_PWREN_CLOCK_ENABLE;
|
||||
|
||||
// Set voltage scaling to "high"
|
||||
PWR->CR &= ~(PWR_CR_VOS_MASK << PWR_CR_VOS_BIT);
|
||||
PWR->CR |= (PWR_SCALE3 << PWR_CR_VOS_BIT);
|
||||
|
||||
// Turn off HSI (which is on by default)
|
||||
RCC->CR &= ~RCC_CR_HSION_ON;
|
||||
|
||||
// Turn on HSE
|
||||
RCC->CR |= RCC_CR_HSEON_ON;
|
||||
|
||||
// Wait indefinitely for HSE to be ready
|
||||
// TODO indicate error/timeout somehow?
|
||||
while (!(RCC->CR & RCC_CR_HSERDY_READY));
|
||||
|
||||
// Disable PLL before changing settings as documentation state
|
||||
// "These bits should be written only if PLL is disabled."
|
||||
RCC->CR &= ~RCC_CR_PLLON_ON;
|
||||
|
||||
// Set HSE as PLL source
|
||||
RCC->PLLCFGR |= RCC_PLLCFGR_PLLSRC_HSE;
|
||||
|
||||
// Settings to achieve system clock of 96Mhz
|
||||
RCC->PLLCFGR |= RCC_PLLCFGR_PLLM(25) | RCC_PLLCFGR_PLLN(192) | RCC_PLLCFGR_PLLP(2) | RCC_PLLCFGR_PLLQ(4);
|
||||
|
||||
// Set AHB prescalar to /1
|
||||
RCC->CFGR &= ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_BIT);
|
||||
RCC->CFGR |= (RCC_CFGR_HPRE_DIV_NONE << RCC_CFGR_HPRE_BIT);
|
||||
|
||||
// Set APB1 prescalar to /2
|
||||
RCC->CFGR &= ~(RCC_CFGR_PPRE1_MASK << RCC_CFGR_PPRE1_BIT);
|
||||
RCC->CFGR |= (RCC_CFGR_PPRE_DIV_2 << RCC_CFGR_PPRE1_BIT);
|
||||
|
||||
// Set APB2 prescalar to /1
|
||||
RCC->CFGR &= ~(RCC_CFGR_PPRE2_MASK << RCC_CFGR_PPRE2_BIT);
|
||||
RCC->CFGR |= (RCC_CFGR_PPRE_DIV_NONE << RCC_CFGR_PPRE2_BIT);
|
||||
|
||||
// Turn PLL back on
|
||||
RCC->CR |= RCC_CR_PLLON_ON;
|
||||
|
||||
// Wait indefinitely for PLL to be ready
|
||||
// TODO indicate error/timeout somehow?
|
||||
while (!(RCC->CR & RCC_CR_PLLRDY_LOCKED));
|
||||
|
||||
// Enable caching of instructions and data
|
||||
FLASH->ACR |= FLASH_ACR_DCEN_ENABLE;
|
||||
FLASH->ACR |= FLASH_ACR_ICEN_ENABLE;
|
||||
|
||||
// TODO breaks with these flash settings on; turning off for now
|
||||
// Set latency to be 3 wait states (TODO: understand why exactly 3)
|
||||
/* FLASH->ACR &= ~(FLASH_ACR_LATENCY_MASK << FLASH_ACR_LATENCY_BIT); */
|
||||
/* RCC->CFGR |= (FLASH_ACR_LATENCY_3_WAIT_STATES << FLASH_ACR_LATENCY_BIT); */
|
||||
|
||||
// Use PLL as system clock
|
||||
RCC->CFGR |= RCC_CFGR_SW(RCC_CFGR_SW_PLL);
|
||||
|
||||
// Wait indefinitely for PLL clock to be selected
|
||||
// TODO indicate error/timeout somehow?
|
||||
while (((RCC->CFGR >> RCC_CFGR_SWS_BIT) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL);
|
||||
}
|
||||
|
||||
int main(void) {
|
||||
(void) system_clock_init();
|
||||
(void) tim4_init();
|
||||
(void) usart2_init();
|
||||
|
||||
(void) tim4_start();
|
||||
(void) usart2_start();
|
||||
|
||||
uint16_t led = PIN('C', 13); // Blue LED
|
||||
RCC->AHB1ENR |= BIT(PINPORT(led)); // Enable GPIO clock for LED
|
||||
RCC->AHB1ENR |= (1 << PINPORT(led)); // Enable GPIO clock for LED
|
||||
gpio_set_mode(led, GPIO_MODE_OUTPUT); // Set blue LED to output mode
|
||||
for (;;) {
|
||||
gpio_write(led, true);
|
||||
spin(999999);
|
||||
gpio_write(led, false);
|
||||
spin(999999);
|
||||
|
||||
uint16_t counter = TIM4->CNT;
|
||||
bool led_on = false;
|
||||
while(1) {
|
||||
if ((TIM4->CNT - counter) >= 250) {
|
||||
led_on = !led_on;
|
||||
gpio_write(led, led_on);
|
||||
|
||||
usart2_write("hello, world!\n");
|
||||
|
||||
counter = TIM4->CNT;
|
||||
}
|
||||
};
|
||||
|
||||
return exit;
|
||||
|
||||
@@ -0,0 +1,22 @@
|
||||
#ifndef PWR_H_
|
||||
#define PWR_H_
|
||||
|
||||
#include <inttypes.h>
|
||||
|
||||
struct pwr {
|
||||
volatile uint32_t CR; // Power control register
|
||||
volatile uint32_t CSR; // Power control/status registe
|
||||
};
|
||||
|
||||
#define PWR_BASE_ADDR (0x40007000U)
|
||||
#define PWR ((struct pwr *) PWR_BASE_ADDR)
|
||||
|
||||
// Power control register
|
||||
#define PWR_SCALE3 (0b11)
|
||||
|
||||
// Regulator voltage scaling output selection
|
||||
#define PWR_CR_VOS_BIT 14 // Bits [15:14]
|
||||
#define PWR_CR_VOS_MASK (0b11)
|
||||
#define PWR_CR_VOS(scale) ((scale & PWR_CR_VOS_MASK) << PWR_CR_VOS_BIT)
|
||||
|
||||
#endif
|
||||
@@ -37,4 +37,104 @@ struct rcc {
|
||||
#define RCC_BASE_ADDR (0x40023800U)
|
||||
#define RCC ((struct rcc *) RCC_BASE_ADDR)
|
||||
|
||||
// CR Register
|
||||
// PLL ready flag
|
||||
#define RCC_CR_PLLRDY_BIT 25
|
||||
#define RCC_CR_PLLRDY_LOCKED (1 << RCC_CR_PLLRDY_BIT)
|
||||
|
||||
// PLL toggle
|
||||
#define RCC_CR_PLLON_BIT 24
|
||||
#define RCC_CR_PLLON_ON (1 << RCC_CR_PLLON_BIT)
|
||||
|
||||
// HSE clock ready flag
|
||||
#define RCC_CR_HSERDY_BIT 17
|
||||
#define RCC_CR_HSERDY_READY (1 << RCC_CR_HSERDY_BIT)
|
||||
|
||||
// HSE clock enable
|
||||
#define RCC_CR_HSEON_BIT 16
|
||||
#define RCC_CR_HSEON_ON (1 << RCC_CR_HSEON_BIT)
|
||||
|
||||
// HSI clock ready flag
|
||||
#define RCC_CR_HSIRDY_BIT 1
|
||||
#define RCC_CR_HSIRDY_READY (1 << RCC_CR_HSIRDY_BIT)
|
||||
|
||||
// HSI clock enable
|
||||
#define RCC_CR_HSION_BIT 0
|
||||
#define RCC_CR_HSION_ON (1 << RCC_CR_HSION_BIT)
|
||||
|
||||
// PLLCFGR Register
|
||||
#define RCC_PLLCFGR_PLLQ_BIT 24 // Bits [27:24]
|
||||
#define RCC_PLLCFGR_PLLQ_MASK (0b1111)
|
||||
#define RCC_PLLCFGR_PLLQ(q) ((q & RCC_PLLCFGR_PLLQ_MASK) << RCC_PLLCFGR_PLLQ_BIT)
|
||||
|
||||
#define RCC_PLLCFGR_PLLSRC_BIT 22
|
||||
#define RCC_PLLCFGR_PLLSRC_HSE (1 << RCC_PLLCFGR_PLLSRC_BIT)
|
||||
|
||||
#define RCC_PLLCFGR_PLLP_BIT 16 // Bits [17:16]
|
||||
#define RCC_PLLCFGR_PLLP_MASK (0b11)
|
||||
#define RCC_PLLCFGR_PLLP(p) ((p & RCC_PLLCFGR_PLLP_MASK) << RCC_PLLCFGR_PLLP_BIT)
|
||||
|
||||
#define RCC_PLLCFGR_PLLN_BIT 6 // Bits [14:6]
|
||||
#define RCC_PLLCFGR_PLLN_MASK (0b111111111)
|
||||
#define RCC_PLLCFGR_PLLN(n) ((n & RCC_PLLCFGR_PLLN_MASK) << RCC_PLLCFGR_PLLN_BIT)
|
||||
|
||||
#define RCC_PLLCFGR_PLLM_BIT 0 // Bits [5:0]
|
||||
#define RCC_PLLCFGR_PLLM_MASK (0b111111)
|
||||
#define RCC_PLLCFGR_PLLM(m) ((m & RCC_PLLCFGR_PLLM_MASK) << RCC_PLLCFGR_PLLM_BIT)
|
||||
|
||||
// CFGR Register
|
||||
// APB{1,2} prescalar
|
||||
#define RCC_CFGR_PPRE_DIV_NONE 0
|
||||
#define RCC_CFGR_PPRE_DIV_2 (0b100)
|
||||
|
||||
// Microcontroller clock output 1
|
||||
#define RCC_CFGR_MCO1_HSE (0b10)
|
||||
#define RCC_CFGR_MCO1_PLL (0b11)
|
||||
|
||||
#define RCC_CFGR_MCO1_BIT 21 // Bits [22:21]
|
||||
#define RCC_CFGR_MCO1_MASK (0b11)
|
||||
|
||||
#define RCC_CFGR_MCO1PRE_DIV4 (0b110)
|
||||
#define RCC_CFGR_MCO1PRE_DIV2 (0b100)
|
||||
|
||||
#define RCC_CFGR_MCO1PRE_BIT 24 // Bits [26:24]
|
||||
#define RCC_CFGR_MCO1PRE_MASK (0b111)
|
||||
|
||||
// APB2
|
||||
#define RCC_CFGR_PPRE2_BIT 13 // Bits [15:13]
|
||||
#define RCC_CFGR_PPRE2_MASK (0b111)
|
||||
|
||||
// APB1
|
||||
#define RCC_CFGR_PPRE1_BIT 10 // Bits [12:10]
|
||||
#define RCC_CFGR_PPRE1_MASK (0b111)
|
||||
|
||||
// AHB prescalar
|
||||
#define RCC_CFGR_HPRE_DIV_NONE 0
|
||||
|
||||
#define RCC_CFGR_HPRE_BIT 4 // Bits [7:4]
|
||||
#define RCC_CFGR_HPRE_MASK (0b1111)
|
||||
|
||||
//System clock switch status
|
||||
#define RCC_CFGR_SWS_PLL (0b10)
|
||||
|
||||
#define RCC_CFGR_SWS_BIT 2 // Bits [3:2]
|
||||
#define RCC_CFGR_SWS_MASK (0b11)
|
||||
|
||||
// System clock switch
|
||||
#define RCC_CFGR_SW_PLL (0b10)
|
||||
|
||||
#define RCC_CFGR_SW_BIT 0 // Bits [1:0]
|
||||
#define RCC_CFGR_SW_MASK (0b11)
|
||||
#define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT)
|
||||
|
||||
// APB1ENR Register
|
||||
#define RCC_APB1ENR_PWREN_BIT 28
|
||||
#define RCC_APB1ENR_PWREN_CLOCK_ENABLE (1 << RCC_APB1ENR_PWREN_BIT)
|
||||
|
||||
#define RCC_APB1ENR_USART2EN_BIT 17
|
||||
#define RCC_APB1ENR_USART2EN_ENABLE (1 << RCC_APB1ENR_USART2EN_BIT)
|
||||
|
||||
#define RCC_APB1ENR_TIM4_BIT 2
|
||||
#define RCC_APB1ENR_TIM4_ENABLE (1 << RCC_APB1ENR_TIM4_BIT)
|
||||
|
||||
#endif
|
||||
|
||||
+22
@@ -0,0 +1,22 @@
|
||||
#include "rcc.h"
|
||||
#include "timer.h"
|
||||
|
||||
void tim4_init(void) {
|
||||
// Enable timer
|
||||
RCC->APB1ENR |= RCC_APB1ENR_TIM4_ENABLE;
|
||||
|
||||
// Reset timer
|
||||
TIM4->CR1 = 0x0000;
|
||||
TIM4->CR2 = 0x0000;
|
||||
|
||||
// Set prescaler
|
||||
// f_clk = 96MHz -> 96E6/96E3 = 1E3 = 1KHz counting frequency = 1ms
|
||||
TIM4->PSC = (uint16_t) 96000 - 1;
|
||||
|
||||
// Set ARR to maximum value to get 1ms between updates
|
||||
TIM4->ARR = (uint16_t) 0xFFFF;
|
||||
}
|
||||
|
||||
void tim4_start(void) {
|
||||
TIM4->CR1 |= TIM_ENABLE;
|
||||
}
|
||||
+38
@@ -0,0 +1,38 @@
|
||||
#ifndef TIMER_H_
|
||||
#define TIMER_H_
|
||||
|
||||
#include <inttypes.h>
|
||||
|
||||
struct timer {
|
||||
volatile uint32_t CR1; // Control register 1
|
||||
volatile uint32_t CR2; // Control register 2
|
||||
volatile uint32_t SMCR; // Slave mode control register
|
||||
volatile uint32_t DIER; // DMA/interrupt enable registe
|
||||
volatile uint32_t SR; // Status register
|
||||
volatile uint32_t EGR; // Event generation register
|
||||
volatile uint32_t CCMR1; // Capture/compare mode register 1
|
||||
volatile uint32_t CCMR2; // Capture/compare mode register 2
|
||||
volatile uint32_t CCER; // Capture/compare enable register
|
||||
volatile uint32_t CNT; // Counter
|
||||
volatile uint32_t PSC; // Prescalar
|
||||
volatile uint32_t ARR; // Auto-reload register
|
||||
volatile uint32_t RCR; // Repetition counter registe
|
||||
volatile uint32_t CCR1; // Capture/compare register 1
|
||||
volatile uint32_t CCR2; // Capture/compare register 2
|
||||
volatile uint32_t CCR3; // Capture/compare register 3
|
||||
volatile uint32_t CCR4; // Capture/compare register 4
|
||||
volatile uint32_t BDTR; // Break and dead-time register
|
||||
volatile uint32_t DCR; // DMA control register
|
||||
volatile uint32_t DMAR; // DMA address for full transfer
|
||||
};
|
||||
|
||||
#define TIM4_BASE_ADDR (0x40000800U)
|
||||
#define TIM4 ((struct timer *) TIM4_BASE_ADDR)
|
||||
|
||||
#define TIM_CR1_CEN_BIT 0
|
||||
#define TIM_ENABLE (1 << TIM_CR1_CEN_BIT)
|
||||
|
||||
void tim4_init(void);
|
||||
void tim4_start(void);
|
||||
|
||||
#endif
|
||||
+75
@@ -0,0 +1,75 @@
|
||||
#include "rcc.h"
|
||||
#include "gpio.h"
|
||||
#include "usart.h"
|
||||
|
||||
void usart2_init(void) {
|
||||
// Enable clock for GPIOA as USART2 is on PORT A pins
|
||||
RCC->AHB1ENR |= (1 << PORT('A'));
|
||||
|
||||
// Configure PA2 and PA3 (USART2 pins) to use alternative functions
|
||||
uint16_t txPin = PIN('A', 2);
|
||||
gpio_set_mode(txPin, GPIO_MODE_AF);
|
||||
gpio_set_af(txPin, GPIO_AF_USART2_TX);
|
||||
|
||||
uint16_t rxPin = PIN('A', 3);
|
||||
gpio_set_mode(rxPin, GPIO_MODE_AF);
|
||||
gpio_set_af(rxPin, GPIO_AF_USART2_RX);
|
||||
|
||||
// Enable MC01; for debugging
|
||||
/* uint16_t clockOutPin = PIN('A', 8); */
|
||||
/* gpio_set_mode(clockOutPin, GPIO_MODE_AF); */
|
||||
/* gpio_set_af(clockOutPin, GPIO_AF_MCO_1); */
|
||||
/* RCC->CFGR &= ~(RCC_CFGR_MCO1_MASK << RCC_CFGR_MCO1_BIT); */
|
||||
/* RCC->CFGR |= (RCC_CFGR_MCO1_HSE << RCC_CFGR_MCO1_BIT); */
|
||||
/* RCC->CFGR |= (RCC_CFGR_MCO1_PLL << RCC_CFGR_MCO1_BIT); */
|
||||
/* RCC->CFGR &= ~(RCC_CFGR_MCO1PRE_MASK << RCC_CFGR_MCO1PRE_BIT); */
|
||||
/* RCC->CFGR |= (RCC_CFGR_MCO1PRE_DIV4 << RCC_CFGR_MCO1PRE_BIT); */
|
||||
|
||||
// Enable USART
|
||||
RCC->APB1ENR |= RCC_APB1ENR_USART2EN_ENABLE;
|
||||
|
||||
// Clear control registers
|
||||
USART2->CR1 = 0;
|
||||
USART2->CR2 = 0;
|
||||
USART2->CR3 = 0;
|
||||
|
||||
// Calculate Baud rate:
|
||||
// baud = f_clck / (8 * (2 - OVER8) * USARTDIV) =>
|
||||
// (8 * (2 - OVER8) * USARTDIV) = f_clock / baud =>
|
||||
// baud * (8 * (2 - OVER8) * USARTDIV) = f_clock =>
|
||||
// USARTDIV = (f_clock / (baud * (8 * (2 - OVER8)))
|
||||
|
||||
// Target Baud rate = 115200, f_clock = 48MHz, OVER8 = 0
|
||||
// USARTDIV = 48E6 / (115200 * 8 * 2) = 26.0416666
|
||||
// mantissa = 26 = 0x1A
|
||||
// fraction = 0.041666 * 16 = 0.666656 ~= 1
|
||||
|
||||
// baud = 48E6 / (8 * 2 * 26) = 115384.61538461539
|
||||
// error of 0.16% (115384.61538461539 / 115200 ) = 1.001602564102564
|
||||
//
|
||||
// skipping fractional part as error rate is good.
|
||||
|
||||
USART2->BRR &= ~(USART_BRR_MANTISSA_MASK << USART_BRR_MANTISSA_BIT);
|
||||
USART2->BRR |= (0x1A << USART_BRR_MANTISSA_BIT);
|
||||
USART2->BRR &= ~(USART_BRR_FRACTION_MASK << USART_BRR_FRACTION_BIT);
|
||||
USART2->BRR |= (0x0 << USART_BRR_MANTISSA_BIT);
|
||||
|
||||
// Enable transmitter and receiver
|
||||
USART2->CR1 |= USART_CR1_TE_ENABLE;
|
||||
USART2->CR1 |= USART_CR1_RE_ENABLE;
|
||||
}
|
||||
|
||||
void usart2_start(void) {
|
||||
USART2->CR1 |= USART_CR1_UE_ENABLE;
|
||||
}
|
||||
|
||||
void usart2_write_byte(uint8_t c) {
|
||||
USART2->DR = c;
|
||||
|
||||
// Wait indefinitely for transmission to be ready for data
|
||||
while (!(USART2->SR & USART_SR_TC_COMPLETED));
|
||||
}
|
||||
|
||||
void usart2_write(char *buf) {
|
||||
while (*buf) usart2_write_byte(*buf++);
|
||||
}
|
||||
+50
@@ -0,0 +1,50 @@
|
||||
#ifndef USART_H_
|
||||
#define USART_H_
|
||||
|
||||
#include <inttypes.h>
|
||||
|
||||
struct usart {
|
||||
volatile uint32_t SR; // Status register
|
||||
volatile uint32_t DR; // Data register
|
||||
volatile uint32_t BRR; // Baud rate register
|
||||
volatile uint32_t CR1; // Control register 1
|
||||
volatile uint32_t CR2; // Control register 2
|
||||
volatile uint32_t CR3; // Control register 3
|
||||
volatile uint32_t GTPR; // Guard time and prescaler register
|
||||
};
|
||||
|
||||
#define USART2_BASE_ADDR (0x40004400U)
|
||||
#define USART2 ((struct usart *) USART2_BASE_ADDR)
|
||||
|
||||
// SR Register
|
||||
// Transmission complete
|
||||
#define USART_SR_TC_BIT 6
|
||||
#define USART_SR_TC_COMPLETED (1 << USART_SR_TC_BIT)
|
||||
|
||||
// CR Register
|
||||
// USART enable
|
||||
#define USART_CR1_UE_BIT 13
|
||||
#define USART_CR1_UE_ENABLE (1 << USART_CR1_UE_BIT)
|
||||
|
||||
// Trasmitter enable
|
||||
#define USART_CR1_TE_BIT 3
|
||||
#define USART_CR1_TE_ENABLE (1 << USART_CR1_TE_BIT)
|
||||
|
||||
// Receiver enable
|
||||
#define USART_CR1_RE_BIT 2
|
||||
#define USART_CR1_RE_ENABLE (1 << USART_CR1_RE_BIT)
|
||||
|
||||
// BRR Register
|
||||
#define USART_BRR_MANTISSA_BIT 4 // Bits [15:4]
|
||||
#define USART_BRR_MANTISSA_MASK (0b111111111111)
|
||||
|
||||
#define USART_BRR_FRACTION_BIT 0 // Bits [3:0]
|
||||
#define USART_BRR_FRACTION_MASK (0b111)
|
||||
|
||||
void usart2_init(void);
|
||||
void usart2_start(void);
|
||||
|
||||
void usart2_write_byte(uint8_t byte);
|
||||
void usart2_write(char *buf);
|
||||
|
||||
#endif
|
||||
+18
@@ -0,0 +1,18 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
#
|
||||
# STMicroelectronics ST-LINK/V1, ST-LINK/V2, ST-LINK/V2-1, STLINK-V3 in-circuit
|
||||
# debugger/programmer
|
||||
#
|
||||
|
||||
adapter driver hla
|
||||
hla_layout stlink
|
||||
hla_device_desc "ST-LINK"
|
||||
hla_vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753 0x0483 0x3754
|
||||
|
||||
# Optionally specify the serial number of ST-LINK/V2 usb device. ST-LINK/V2
|
||||
# devices seem to have serial numbers with unreadable characters. ST-LINK/V2
|
||||
# firmware version >= V2.J21.S4 recommended to avoid issues with adapter serial
|
||||
# number reset issues.
|
||||
# eg.
|
||||
# adapter serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f"
|
||||
+148
@@ -0,0 +1,148 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
# script for stm32f4x family
|
||||
|
||||
#
|
||||
# stm32f4 devices support both JTAG and SWD transports.
|
||||
#
|
||||
source [find target/swj-dp.tcl]
|
||||
source [find mem_helper.tcl]
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME stm32f4x
|
||||
}
|
||||
|
||||
set _ENDIAN little
|
||||
|
||||
# Work-area is a space in RAM used for flash programming
|
||||
# By default use 32kB (Available RAM in smallest device STM32F410)
|
||||
if { [info exists WORKAREASIZE] } {
|
||||
set _WORKAREASIZE $WORKAREASIZE
|
||||
} else {
|
||||
set _WORKAREASIZE 0x8000
|
||||
}
|
||||
|
||||
#jtag scan chain
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
if { [using_jtag] } {
|
||||
# See STM Document RM0090
|
||||
# Section 38.6.3 - corresponds to Cortex-M4 r0p1
|
||||
set _CPUTAPID 0x4ba00477
|
||||
} {
|
||||
set _CPUTAPID 0x2ba01477
|
||||
}
|
||||
}
|
||||
|
||||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
|
||||
|
||||
if {[using_jtag]} {
|
||||
jtag newtap $_CHIPNAME bs -irlen 5
|
||||
}
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
|
||||
|
||||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
|
||||
|
||||
set _FLASHNAME $_CHIPNAME.flash
|
||||
flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
|
||||
|
||||
flash bank $_CHIPNAME.otp stm32f2x 0x1fff7800 0 0 0 $_TARGETNAME
|
||||
|
||||
if { [info exists QUADSPI] && $QUADSPI } {
|
||||
set a [llength [flash list]]
|
||||
set _QSPINAME $_CHIPNAME.qspi
|
||||
flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
|
||||
}
|
||||
|
||||
# JTAG speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
|
||||
#
|
||||
# Since we may be running of an RC oscilator, we crank down the speed a
|
||||
# bit more to be on the safe side. Perhaps superstition, but if are
|
||||
# running off a crystal, we can run closer to the limit. Note
|
||||
# that there can be a pretty wide band where things are more or less stable.
|
||||
adapter speed 2000
|
||||
|
||||
adapter srst delay 100
|
||||
if {[using_jtag]} {
|
||||
jtag_ntrst_delay 100
|
||||
}
|
||||
|
||||
reset_config srst_nogate
|
||||
|
||||
if {![using_hla]} {
|
||||
# if srst is not fitted use SYSRESETREQ to
|
||||
# perform a soft reset
|
||||
cortex_m reset_config sysresetreq
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event examine-end {
|
||||
# Enable debug during low power modes (uses more power)
|
||||
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
|
||||
mmw 0xE0042004 0x00000007 0
|
||||
|
||||
# Stop watchdog counters during halt
|
||||
# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
|
||||
mmw 0xE0042008 0x00001800 0
|
||||
}
|
||||
|
||||
tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
|
||||
|
||||
lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
|
||||
proc _proc_pre_enable_$_CHIPNAME.tpiu {_chipname} {
|
||||
targets $_chipname.cpu
|
||||
|
||||
if { [$_chipname.tpiu cget -protocol] eq "sync" } {
|
||||
switch [$_chipname.tpiu cget -port-width] {
|
||||
1 {
|
||||
# Set TRACE_IOEN; TRACE_MODE to sync 1 bit; GPIOE[2-3] to AF0
|
||||
mmw 0xE0042004 0x00000060 0x000000c0
|
||||
mmw 0x40021020 0x00000000 0x0000ff00
|
||||
mmw 0x40021000 0x000000a0 0x000000f0
|
||||
mmw 0x40021008 0x000000f0 0x00000000
|
||||
}
|
||||
2 {
|
||||
# Set TRACE_IOEN; TRACE_MODE to sync 2 bit; GPIOE[2-4] to AF0
|
||||
mmw 0xE0042004 0x000000a0 0x000000c0
|
||||
mmw 0x40021020 0x00000000 0x000fff00
|
||||
mmw 0x40021000 0x000002a0 0x000003f0
|
||||
mmw 0x40021008 0x000003f0 0x00000000
|
||||
}
|
||||
4 {
|
||||
# Set TRACE_IOEN; TRACE_MODE to sync 4 bit; GPIOE[2-6] to AF0
|
||||
mmw 0xE0042004 0x000000e0 0x000000c0
|
||||
mmw 0x40021020 0x00000000 0x0fffff00
|
||||
mmw 0x40021000 0x00002aa0 0x00003ff0
|
||||
mmw 0x40021008 0x00003ff0 0x00000000
|
||||
}
|
||||
}
|
||||
} else {
|
||||
# Set TRACE_IOEN; TRACE_MODE to async
|
||||
mmw 0xE0042004 0x00000020 0x000000c0
|
||||
}
|
||||
}
|
||||
|
||||
$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_CHIPNAME"
|
||||
|
||||
$_TARGETNAME configure -event reset-init {
|
||||
# Configure PLL to boost clock to HSI x 4 (64 MHz)
|
||||
mww 0x40023804 0x08012008 ;# RCC_PLLCFGR 16 Mhz /8 (M) * 128 (N) /4(P)
|
||||
mww 0x40023C00 0x00000102 ;# FLASH_ACR = PRFTBE | 2(Latency)
|
||||
mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON
|
||||
sleep 10 ;# Wait for PLL to lock
|
||||
mmw 0x40023808 0x00001000 0 ;# RCC_CFGR |= RCC_CFGR_PPRE1_DIV2
|
||||
mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
|
||||
|
||||
# Boost JTAG frequency
|
||||
adapter speed 8000
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event reset-start {
|
||||
# Reduce speed since CPU speed will slow down to 16MHz with the reset
|
||||
adapter speed 2000
|
||||
}
|
||||
Reference in New Issue
Block a user