Add README

As it blocks the mc from reaching a ready state for unknown reason(s)

README.md

@@ -0,0 +1,35 @@
+# Falling sand on the STM32F411CE
+
+## Building
+Run
+```sh
+make build
+```
+
+## Probe for the board
+Run
+```sh
+st-info --probe
+```
+
+## Flashing
+Run
+```sh
+make flash
+```
+
+## Debugging
+
+### `st-info --probe` shows 0KB flash
+```
+> sudo st-info --probe
+Found 1 stlink programmers
+  version:    V2J43S28
+  serial:     0671FF343056363043090732
+  flash:      0 (pagesize: 16384)      <--- 0KB flash
+  sram:       131072
+  chipid:     0x431
+  dev-type:   STM32F411xC_xE
+```
+This can happen when the flash is locked. One way to unlock it is to erase the entire chip via the
+Windows application `ST-Link Util`.

build/final.elf.map

@@ -53,7 +53,7 @@ Discarded input sections
  .debug_macro   0x00000000       0x89 build/main.o
  .debug_macro   0x00000000      0x4cc build/main.o
  .debug_macro   0x00000000       0x22 build/main.o
- .debug_macro   0x00000000       0x88 build/main.o
+ .debug_macro   0x00000000       0x46 build/main.o
  .group         0x00000000        0xc build/startup.o
  .group         0x00000000        0xc build/startup.o
  .group         0x00000000        0xc build/startup.o
@@ -128,9 +128,9 @@ Discarded input sections
  .debug_macro   0x00000000      0x1df build/usart.o
  .debug_macro   0x00000000       0x89 build/usart.o
  .debug_macro   0x00000000      0x4cc build/usart.o
- .debug_macro   0x00000000      0x13e build/usart.o
+ .debug_macro   0x00000000      0x167 build/usart.o
  .debug_macro   0x00000000       0x22 build/usart.o
- .debug_macro   0x00000000       0x76 build/usart.o
+ .debug_macro   0x00000000       0x5e build/usart.o
 
 Memory Configuration
 
@@ -157,135 +157,144 @@ LOAD build/usart.o
                 0x08000000                interrupt_vector_table
                 0x08000198                        . = ALIGN (0x4)
 
-.text           0x08000198      0x4b0
+.text           0x08000198      0x520
                 0x08000198                        . = ALIGN (0x4)
  *(.text)
  *(.text.*)
  .text.gpio_set_mode
                 0x08000198       0x62 build/gpio.o
                 0x08000198                gpio_set_mode
+ .text.gpio_set_af
+                0x080001fa       0x98 build/gpio.o
+                0x080001fa                gpio_set_af
  .text.gpio_write
-                0x080001fa       0x4c build/gpio.o
-                0x080001fa                gpio_write
- *fill*         0x08000246        0x2 
+                0x08000292       0x4c build/gpio.o
+                0x08000292                gpio_write
+ *fill*         0x080002de        0x2 
  .text.system_clock_init
-                0x08000248      0x144 build/main.o
- .text.main     0x0800038c       0x98 build/main.o
-                0x0800038c                main
+                0x080002e0      0x11c build/main.o
+ .text.main     0x080003fc       0x9c build/main.o
+                0x080003fc                main
  .text.init_memory
-                0x08000424       0x64 build/startup.o
-                0x08000424                init_memory
- .text.reset    0x08000488       0x10 build/startup.o
-                0x08000488                reset
+                0x08000498       0x64 build/startup.o
+                0x08000498                init_memory
+ .text.reset    0x080004fc       0x10 build/startup.o
+                0x080004fc                reset
  .text.default_handler
-                0x08000498        0x8 build/startup.o
-                0x08000498                exti0
-                0x08000498                debug_monitor
-                0x08000498                rcc
-                0x08000498                x
-                0x08000498                sdio
-                0x08000498                usage_fault
-                0x08000498                tim1_up_tim10
-                0x08000498                usart1
-                0x08000498                i2c3_er
-                0x08000498                spi2
-                0x08000498                dma1_stream1
-                0x08000498                bus_fault
-                0x08000498                spi5
-                0x08000498                exti3
-                0x08000498                dma2_stream5
-                0x08000498                tim2
-                0x08000498                dma1_stream6
-                0x08000498                default_handler
-                0x08000498                i2c1_er
-                0x08000498                hard_fault
-                0x08000498                usart6
-                0x08000498                exti15_10
-                0x08000498                usart2
-                0x08000498                pend_sv
-                0x08000498                i2c1_ev
-                0x08000498                wwdg
-                0x08000498                adc
-                0x08000498                rtc_alarm
-                0x08000498                spi3
-                0x08000498                exti1
-                0x08000498                mem_manage
-                0x08000498                dma2_stream1
-                0x08000498                dma1_stream2
-                0x08000498                dma2_stream3
-                0x08000498                sv_call
-                0x08000498                tim3
-                0x08000498                otg_fs
-                0x08000498                dma1_stream5
-                0x08000498                dma2_stream6
-                0x08000498                flash
-                0x08000498                tamp_stamp
-                0x08000498                i2c3_ev
-                0x08000498                rtc_wkup
-                0x08000498                dma2_stream0
-                0x08000498                pvd
-                0x08000498                fpu
-                0x08000498                exti4
-                0x08000498                exti2
-                0x08000498                spi1
-                0x08000498                dma1_stream0
-                0x08000498                tim1_brk_tim9
-                0x08000498                i2c2_ev
-                0x08000498                otg_fs_wkup
-                0x08000498                spi4
-                0x08000498                dma2_stream2
-                0x08000498                tim1_cc
-                0x08000498                tim1_trg_com_tim11
-                0x08000498                exti9_5
-                0x08000498                dma1_stream3
-                0x08000498                dma2_stream4
-                0x08000498                i2c2_er
-                0x08000498                dma2_stream7
-                0x08000498                dma1_stream7
-                0x08000498                nmi
-                0x08000498                systick
-                0x08000498                tim4
-                0x08000498                tim5
-                0x08000498                dma1_stream4
+                0x0800050c        0x8 build/startup.o
+                0x0800050c                exti0
+                0x0800050c                debug_monitor
+                0x0800050c                rcc
+                0x0800050c                x
+                0x0800050c                sdio
+                0x0800050c                usage_fault
+                0x0800050c                tim1_up_tim10
+                0x0800050c                usart1
+                0x0800050c                i2c3_er
+                0x0800050c                spi2
+                0x0800050c                dma1_stream1
+                0x0800050c                bus_fault
+                0x0800050c                spi5
+                0x0800050c                exti3
+                0x0800050c                dma2_stream5
+                0x0800050c                tim2
+                0x0800050c                dma1_stream6
+                0x0800050c                default_handler
+                0x0800050c                i2c1_er
+                0x0800050c                hard_fault
+                0x0800050c                usart6
+                0x0800050c                exti15_10
+                0x0800050c                usart2
+                0x0800050c                pend_sv
+                0x0800050c                i2c1_ev
+                0x0800050c                wwdg
+                0x0800050c                adc
+                0x0800050c                rtc_alarm
+                0x0800050c                spi3
+                0x0800050c                exti1
+                0x0800050c                mem_manage
+                0x0800050c                dma2_stream1
+                0x0800050c                dma1_stream2
+                0x0800050c                dma2_stream3
+                0x0800050c                sv_call
+                0x0800050c                tim3
+                0x0800050c                otg_fs
+                0x0800050c                dma1_stream5
+                0x0800050c                dma2_stream6
+                0x0800050c                flash
+                0x0800050c                tamp_stamp
+                0x0800050c                i2c3_ev
+                0x0800050c                rtc_wkup
+                0x0800050c                dma2_stream0
+                0x0800050c                pvd
+                0x0800050c                fpu
+                0x0800050c                exti4
+                0x0800050c                exti2
+                0x0800050c                spi1
+                0x0800050c                dma1_stream0
+                0x0800050c                tim1_brk_tim9
+                0x0800050c                i2c2_ev
+                0x0800050c                otg_fs_wkup
+                0x0800050c                spi4
+                0x0800050c                dma2_stream2
+                0x0800050c                tim1_cc
+                0x0800050c                tim1_trg_com_tim11
+                0x0800050c                exti9_5
+                0x0800050c                dma1_stream3
+                0x0800050c                dma2_stream4
+                0x0800050c                i2c2_er
+                0x0800050c                dma2_stream7
+                0x0800050c                dma1_stream7
+                0x0800050c                nmi
+                0x0800050c                systick
+                0x0800050c                tim4
+                0x0800050c                tim5
+                0x0800050c                dma1_stream4
  .text.tim4_init
-                0x080004a0       0x40 build/timer.o
-                0x080004a0                tim4_init
+                0x08000514       0x40 build/timer.o
+                0x08000514                tim4_init
  .text.tim4_start
-                0x080004e0       0x20 build/timer.o
-                0x080004e0                tim4_start
+                0x08000554       0x20 build/timer.o
+                0x08000554                tim4_start
  .text.usart2_init
-                0x08000500       0xf8 build/usart.o
-                0x08000500                usart2_init
+                0x08000574       0xb8 build/usart.o
+                0x08000574                usart2_init
  .text.usart2_start
-                0x080005f8       0x20 build/usart.o
-                0x080005f8                usart2_start
+                0x0800062c       0x20 build/usart.o
+                0x0800062c                usart2_start
  .text.usart2_write_byte
-                0x08000618       0x30 build/usart.o
-                0x08000618                usart2_write_byte
+                0x0800064c       0x30 build/usart.o
+                0x0800064c                usart2_write_byte
+ .text.usart2_write
+                0x0800067c       0x2a build/usart.o
+                0x0800067c                usart2_write
  *(.rodata)
+ *fill*         0x080006a6        0x2 
+ .rodata        0x080006a8        0xf build/main.o
  *(.rodata.*)
-                0x08000648                        . = ALIGN (0x4)
-                0x08000648                        _data_addr = LOADADDR (.data)
+                0x080006b8                        . = ALIGN (0x4)
+ *fill*         0x080006b7        0x1 
+                0x080006b8                        _data_addr = LOADADDR (.data)
 
-.glue_7         0x08000648        0x0
- .glue_7        0x08000648        0x0 linker stubs
+.glue_7         0x080006b8        0x0
+ .glue_7        0x080006b8        0x0 linker stubs
 
-.glue_7t        0x08000648        0x0
- .glue_7t       0x08000648        0x0 linker stubs
+.glue_7t        0x080006b8        0x0
+ .glue_7t       0x080006b8        0x0 linker stubs
 
-.vfp11_veneer   0x08000648        0x0
- .vfp11_veneer  0x08000648        0x0 linker stubs
+.vfp11_veneer   0x080006b8        0x0
+ .vfp11_veneer  0x080006b8        0x0 linker stubs
 
-.v4_bx          0x08000648        0x0
- .v4_bx         0x08000648        0x0 linker stubs
+.v4_bx          0x080006b8        0x0
+ .v4_bx         0x080006b8        0x0 linker stubs
 
-.iplt           0x08000648        0x0
- .iplt          0x08000648        0x0 build/main.o
+.iplt           0x080006b8        0x0
+ .iplt          0x080006b8        0x0 build/main.o
 
-.rel.dyn        0x08000648        0x0
- .rel.iplt      0x08000648        0x0 build/main.o
+.rel.dyn        0x080006b8        0x0
+ .rel.iplt      0x080006b8        0x0 build/main.o
 
-.data           0x20000000        0x0 load address 0x08000648
+.data           0x20000000        0x0 load address 0x080006b8
                 0x20000000                        . = ALIGN (0x4)
                 0x20000000                        _data_start = .
  *(.data)
@@ -293,10 +302,10 @@ LOAD build/usart.o
                 0x20000000                        . = ALIGN (0x4)
                 0x20000000                        _data_end = .
 
-.igot.plt       0x20000000        0x0 load address 0x08000648
+.igot.plt       0x20000000        0x0 load address 0x080006b8
  .igot.plt      0x20000000        0x0 build/main.o
 
-.bss            0x20000000        0x0 load address 0x08000648
+.bss            0x20000000        0x0 load address 0x080006b8
                 0x20000000                        . = ALIGN (0x4)
                 0x20000000                        _bss_start = .
  *(.bss)
@@ -306,46 +315,46 @@ LOAD build/usart.o
 OUTPUT(build/final.elf elf32-littlearm)
 LOAD linker stubs
 
-.debug_info     0x00000000      0xe69
- .debug_info    0x00000000      0x205 build/gpio.o
- .debug_info    0x00000205      0x478 build/main.o
- .debug_info    0x0000067d      0x188 build/startup.o
- .debug_info    0x00000805      0x335 build/timer.o
- .debug_info    0x00000b3a      0x32f build/usart.o
+.debug_info     0x00000000      0xf1e
+ .debug_info    0x00000000      0x262 build/gpio.o
+ .debug_info    0x00000262      0x47e build/main.o
+ .debug_info    0x000006e0      0x188 build/startup.o
+ .debug_info    0x00000868      0x335 build/timer.o
+ .debug_info    0x00000b9d      0x381 build/usart.o
 
-.debug_abbrev   0x00000000      0x519
- .debug_abbrev  0x00000000      0x119 build/gpio.o
- .debug_abbrev  0x00000119      0x142 build/main.o
- .debug_abbrev  0x0000025b      0x127 build/startup.o
- .debug_abbrev  0x00000382       0xb5 build/timer.o
- .debug_abbrev  0x00000437       0xe2 build/usart.o
+.debug_abbrev   0x00000000      0x5ae
+ .debug_abbrev  0x00000000      0x11d build/gpio.o
+ .debug_abbrev  0x0000011d      0x14b build/main.o
+ .debug_abbrev  0x00000268      0x127 build/startup.o
+ .debug_abbrev  0x0000038f       0xb5 build/timer.o
+ .debug_abbrev  0x00000444      0x16a build/usart.o
 
-.debug_aranges  0x00000000       0xd8
+.debug_aranges  0x00000000       0xe8
  .debug_aranges
-                0x00000000       0x28 build/gpio.o
+                0x00000000       0x30 build/gpio.o
  .debug_aranges
-                0x00000028       0x28 build/main.o
+                0x00000030       0x28 build/main.o
  .debug_aranges
-                0x00000050       0x30 build/startup.o
+                0x00000058       0x30 build/startup.o
  .debug_aranges
-                0x00000080       0x28 build/timer.o
+                0x00000088       0x28 build/timer.o
  .debug_aranges
-                0x000000a8       0x30 build/usart.o
+                0x000000b0       0x38 build/usart.o
 
 .debug_rnglists
-                0x00000000       0x8c
+                0x00000000       0x99
  .debug_rnglists
-                0x00000000       0x19 build/gpio.o
+                0x00000000       0x20 build/gpio.o
  .debug_rnglists
-                0x00000019       0x1b build/main.o
+                0x00000020       0x1b build/main.o
  .debug_rnglists
-                0x00000034       0x1f build/startup.o
+                0x0000003b       0x1f build/startup.o
  .debug_rnglists
-                0x00000053       0x19 build/timer.o
+                0x0000005a       0x19 build/timer.o
  .debug_rnglists
-                0x0000006c       0x20 build/usart.o
+                0x00000073       0x26 build/usart.o
 
-.debug_macro    0x00000000     0x489d
+.debug_macro    0x00000000     0x4853
  .debug_macro   0x00000000      0xb56 build/gpio.o
  .debug_macro   0x00000b56       0x22 build/gpio.o
  .debug_macro   0x00000b78       0x75 build/gpio.o
@@ -360,39 +369,39 @@ LOAD linker stubs
  .debug_macro   0x0000108c       0x89 build/gpio.o
  .debug_macro   0x00001115      0x4cc build/gpio.o
  .debug_macro   0x000015e1       0x22 build/gpio.o
- .debug_macro   0x00001603       0x88 build/gpio.o
- .debug_macro   0x0000168b      0xb89 build/main.o
- .debug_macro   0x00002214      0x144 build/main.o
- .debug_macro   0x00002358       0x46 build/main.o
- .debug_macro   0x0000239e       0x2e build/main.o
- .debug_macro   0x000023cc       0x22 build/main.o
- .debug_macro   0x000023ee       0x76 build/main.o
- .debug_macro   0x00002464      0xb02 build/startup.o
- .debug_macro   0x00002f66       0x56 build/startup.o
- .debug_macro   0x00002fbc       0x51 build/startup.o
- .debug_macro   0x0000300d      0xb5c build/timer.o
- .debug_macro   0x00003b69      0x13e build/timer.o
- .debug_macro   0x00003ca7      0xb74 build/usart.o
- .debug_macro   0x0000481b       0x82 build/usart.o
+ .debug_macro   0x00001603       0x46 build/gpio.o
+ .debug_macro   0x00001649      0xb89 build/main.o
+ .debug_macro   0x000021d2      0x16d build/main.o
+ .debug_macro   0x0000233f       0x46 build/main.o
+ .debug_macro   0x00002385       0x2e build/main.o
+ .debug_macro   0x000023b3       0x22 build/main.o
+ .debug_macro   0x000023d5       0x5e build/main.o
+ .debug_macro   0x00002433      0xb02 build/startup.o
+ .debug_macro   0x00002f35       0x56 build/startup.o
+ .debug_macro   0x00002f8b       0x51 build/startup.o
+ .debug_macro   0x00002fdc      0xb5c build/timer.o
+ .debug_macro   0x00003b38      0x167 build/timer.o
+ .debug_macro   0x00003c9f      0xb74 build/usart.o
+ .debug_macro   0x00004813       0x40 build/usart.o
 
-.debug_line     0x00000000      0x63b
- .debug_line    0x00000000      0x116 build/gpio.o
- .debug_line    0x00000116      0x1e4 build/main.o
- .debug_line    0x000002fa       0xea build/startup.o
- .debug_line    0x000003e4       0xdf build/timer.o
- .debug_line    0x000004c3      0x178 build/usart.o
+.debug_line     0x00000000      0x691
+ .debug_line    0x00000000      0x179 build/gpio.o
+ .debug_line    0x00000179      0x1d2 build/main.o
+ .debug_line    0x0000034b       0xea build/startup.o
+ .debug_line    0x00000435       0xdf build/timer.o
+ .debug_line    0x00000514      0x17d build/usart.o
 
-.debug_str      0x00000000     0x6393
- .debug_str     0x00000000     0x550b build/gpio.o
-                               0x56b3 (size before relaxing)
- .debug_str     0x0000550b      0xddd build/main.o
-                               0x6440 (size before relaxing)
- .debug_str     0x000062e8       0x88 build/startup.o
-                               0x3cdf (size before relaxing)
- .debug_str     0x00006370        0xc build/timer.o
-                               0x5bc5 (size before relaxing)
- .debug_str     0x0000637c       0x17 build/usart.o
-                               0x6091 (size before relaxing)
+.debug_str      0x00000000     0x626f
+ .debug_str     0x00000000     0x53d8 build/gpio.o
+                               0x5588 (size before relaxing)
+ .debug_str     0x000053d8      0xdce build/main.o
+                               0x62e8 (size before relaxing)
+ .debug_str     0x000061a6       0x88 build/startup.o
+                               0x3cdc (size before relaxing)
+ .debug_str     0x0000622e        0xc build/timer.o
+                               0x5c41 (size before relaxing)
+ .debug_str     0x0000623a       0x35 build/usart.o
+                               0x5fac (size before relaxing)
 
 .comment        0x00000000       0x45
  .comment       0x00000000       0x45 build/gpio.o
@@ -416,26 +425,26 @@ LOAD linker stubs
                 0x000000d0       0x34 build/usart.o
 
 .debug_line_str
-                0x00000000      0x293
+                0x00000000      0x290
  .debug_line_str
-                0x00000000      0x24e build/gpio.o
-                                0x260 (size before relaxing)
+                0x00000000      0x24b build/gpio.o
+                                0x25d (size before relaxing)
  .debug_line_str
-                0x0000024e       0x2b build/main.o
-                                0x284 (size before relaxing)
+                0x0000024b       0x2b build/main.o
+                                0x281 (size before relaxing)
  .debug_line_str
-                0x00000279        0xa build/startup.o
-                                0x21b (size before relaxing)
+                0x00000276        0xa build/startup.o
+                                0x218 (size before relaxing)
  .debug_line_str
-                0x00000283        0x8 build/timer.o
-                                0x25e (size before relaxing)
+                0x00000280        0x8 build/timer.o
+                                0x25b (size before relaxing)
  .debug_line_str
-                0x0000028b        0x8 build/usart.o
-                                0x26f (size before relaxing)
+                0x00000288        0x8 build/usart.o
+                                0x26c (size before relaxing)
 
-.debug_frame    0x00000000      0x1e4
- .debug_frame   0x00000000       0x60 build/gpio.o
- .debug_frame   0x00000060       0x50 build/main.o
- .debug_frame   0x000000b0       0x6c build/startup.o
- .debug_frame   0x0000011c       0x50 build/timer.o
- .debug_frame   0x0000016c       0x78 build/usart.o
+.debug_frame    0x00000000      0x234
+ .debug_frame   0x00000000       0x88 build/gpio.o
+ .debug_frame   0x00000088       0x50 build/main.o
+ .debug_frame   0x000000d8       0x6c build/startup.o
+ .debug_frame   0x00000144       0x50 build/timer.o
+ .debug_frame   0x00000194       0xa0 build/usart.o

build/gpio.i

@@ -1,5 +1,5 @@
 # 0 "src/gpio.c"
-# 1 "/home/alex/code/own/c-compile-experiments//"
+# 1 "/home/alex/code/own/stm32-falling-sand//"
 # 0 "<built-in>"
 #define __STDC__ 1
 # 0 "<built-in>"
@@ -1999,39 +1999,19 @@ struct gpio {
   volatile uint32_t AFRH;
 };
 
-#define GPIOA_BASE_ADDR (0x40020000U)
-#define GPIOA ((struct gpio *) GPIOA_BASE_ADDR)
-
-
-#define GPIO_MODER_MODER3_BIT 7
-#define GPIO_MODER_MODER3_MASK (0b11)
-#define GPIO_MODER_MODER3_AF (0b10)
-
-#define GPIO_MODER_MODER2_BIT 4
-#define GPIO_MODER_MODER2_MASK (0b11)
-#define GPIO_MODER_MODER2_AF (0b10)
-
-
-#define GPIO_AFRL_AFRL3_BIT 12
-#define GPIO_AFRL_AFRL3_MASK (0b1111)
-#define GPIO_AFRL_AFRL3_USART2_RX (0b0111)
-
-#define GPIO_AFRL_AFRL2_BIT 8
-#define GPIO_AFRL_AFRL2_MASK (0b1111)
-#define GPIO_AFRL_AFRL2_USART2_TX (0b0111)
-
-
-
-
 
+#define GPIO_AF_MCO_1 (0b0000)
+#define GPIO_AF_USART2_RX (0b0111)
+#define GPIO_AF_USART2_TX (0b0111)
 
 #define GPIO_BASE_ADDR (0x40020000U)
 #define GPIO_PORT_OFFSET (0x400U)
 #define GPIO(port) ((struct gpio*)(uintptr_t)(GPIO_BASE_ADDR + (GPIO_PORT_OFFSET * port)))
 
-#define BIT(x) (1 << x)
 
-#define PIN(port,num) ((((port) - 'A') << 8) | num)
+#define PORT(port) (((port) - 'A') << 8)
+
+#define PIN(port,num) (PORT(port) | num)
 
 #define PINNUM(pin) (pin & 0b1111)
 
@@ -2045,24 +2025,37 @@ typedef enum {
 } GPIO_MODE;
 
 void gpio_set_mode(uint16_t pin, GPIO_MODE mode);
+void gpio_set_af(uint16_t pin, uint8_t af);
 void gpio_write(uint16_t pin, 
-# 66 "src/gpio.h" 3 4
+# 47 "src/gpio.h" 3 4
                              _Bool 
-# 66 "src/gpio.h"
+# 47 "src/gpio.h"
                                   val);
 # 5 "src/gpio.c" 2
 
 void gpio_set_mode(uint16_t pin, GPIO_MODE mode) {
   struct gpio *gpio = ((struct gpio*)(uintptr_t)((0x40020000U) + ((0x400U) * (pin >> 8))));
   int pn = (pin & 0b1111);
-  gpio->MODER &= ~(0x0011 << (pn * 2));
-  gpio->MODER |= (mode & 0b011) << (pn * 2);
+  gpio->MODER &= ~(0b11 << (pn * 2));
+  gpio->MODER |= (mode & 0b11) << (pn * 2);
+}
+
+void gpio_set_af(uint16_t pin, uint8_t af) {
+  struct gpio *gpio = ((struct gpio*)(uintptr_t)((0x40020000U) + ((0x400U) * (pin >> 8))));
+  int pn = (pin & 0b1111);
+  if (pn < 8) {
+ gpio->AFRL &= ~(0b1111 << (pn * 4));
+ gpio->AFRL |= (af & 0b1111) << (pn * 4);
+  } else {
+ gpio->AFRH &= ~(0b1111 << (pn * 4));
+ gpio->AFRH |= (af & 0b1111) << (pn * 4);
+  }
 }
 
 void gpio_write(uint16_t pin, 
-# 13 "src/gpio.c" 3 4
+# 25 "src/gpio.c" 3 4
                              _Bool 
-# 13 "src/gpio.c"
+# 25 "src/gpio.c"
                                   val) {
   struct gpio *gpio = ((struct gpio*)(uintptr_t)((0x40020000U) + ((0x400U) * (pin >> 8))));
   gpio->BSRR = (0b0011 << (pin & 0b1111)) << (val ? 0 : 16);

build/main.i

@@ -1,5 +1,5 @@
 # 0 "src/main.c"
-# 1 "/home/alex/code/own/c-compile-experiments//"
+# 1 "/home/alex/code/own/stm32-falling-sand//"
 # 0 "<built-in>"
 #define __STDC__ 1
 # 0 "<built-in>"
@@ -2070,6 +2070,19 @@ struct rcc {
 #define RCC_CFGR_PPRE_DIV_2 (0b100)
 
 
+#define RCC_CFGR_MCO1_HSE (0b10)
+#define RCC_CFGR_MCO1_PLL (0b11)
+
+#define RCC_CFGR_MCO1_BIT 21
+#define RCC_CFGR_MCO1_MASK (0b11)
+
+#define RCC_CFGR_MCO1PRE_DIV4 (0b110)
+#define RCC_CFGR_MCO1PRE_DIV2 (0b100)
+
+#define RCC_CFGR_MCO1PRE_BIT 24
+#define RCC_CFGR_MCO1PRE_MASK (0b111)
+
+
 #define RCC_CFGR_PPRE2_BIT 13
 #define RCC_CFGR_PPRE2_MASK (0b111)
 
@@ -2097,11 +2110,6 @@ struct rcc {
 #define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT)
 
 
-
-#define RCC_AHB1ENR_GPIOAEN_BIT 0
-#define RCC_AHB1ENR_GPIOAEN_ENABLE (1 << RCC_AHB1ENR_GPIOAEN_BIT)
-
-
 #define RCC_APB1ENR_PWREN_BIT 28
 #define RCC_APB1ENR_PWREN_CLOCK_ENABLE (1 << RCC_APB1ENR_PWREN_BIT)
 
@@ -2131,39 +2139,19 @@ struct gpio {
   volatile uint32_t AFRH;
 };
 
-#define GPIOA_BASE_ADDR (0x40020000U)
-#define GPIOA ((struct gpio *) GPIOA_BASE_ADDR)
-
-
-#define GPIO_MODER_MODER3_BIT 7
-#define GPIO_MODER_MODER3_MASK (0b11)
-#define GPIO_MODER_MODER3_AF (0b10)
-
-#define GPIO_MODER_MODER2_BIT 4
-#define GPIO_MODER_MODER2_MASK (0b11)
-#define GPIO_MODER_MODER2_AF (0b10)
-
-
-#define GPIO_AFRL_AFRL3_BIT 12
-#define GPIO_AFRL_AFRL3_MASK (0b1111)
-#define GPIO_AFRL_AFRL3_USART2_RX (0b0111)
-
-#define GPIO_AFRL_AFRL2_BIT 8
-#define GPIO_AFRL_AFRL2_MASK (0b1111)
-#define GPIO_AFRL_AFRL2_USART2_TX (0b0111)
-
-
-
-
 
+#define GPIO_AF_MCO_1 (0b0000)
+#define GPIO_AF_USART2_RX (0b0111)
+#define GPIO_AF_USART2_TX (0b0111)
 
 #define GPIO_BASE_ADDR (0x40020000U)
 #define GPIO_PORT_OFFSET (0x400U)
 #define GPIO(port) ((struct gpio*)(uintptr_t)(GPIO_BASE_ADDR + (GPIO_PORT_OFFSET * port)))
 
-#define BIT(x) (1 << x)
 
-#define PIN(port,num) ((((port) - 'A') << 8) | num)
+#define PORT(port) (((port) - 'A') << 8)
+
+#define PIN(port,num) (PORT(port) | num)
 
 #define PINNUM(pin) (pin & 0b1111)
 
@@ -2177,10 +2165,11 @@ typedef enum {
 } GPIO_MODE;
 
 void gpio_set_mode(uint16_t pin, GPIO_MODE mode);
+void gpio_set_af(uint16_t pin, uint8_t af);
 void gpio_write(uint16_t pin, 
-# 66 "src/gpio.h" 3 4
+# 47 "src/gpio.h" 3 4
                              _Bool 
-# 66 "src/gpio.h"
+# 47 "src/gpio.h"
                                   val);
 # 6 "src/main.c" 2
 # 1 "src/flash.h" 1
@@ -2211,7 +2200,7 @@ struct flash {
 #define FLASH_ACR_ICEN_ENABLE (1 <<FLASH_ACR_ICEN_BIT)
 
 
-#define FLASH_ACR_LATENCY_3_WAIT_STATES (0x0111)
+#define FLASH_ACR_LATENCY_3_WAIT_STATES (0b0011)
 
 #define FLASH_ACR_LATENCY_BIT 0
 #define FLASH_ACR_LATENCY_MASK (0b1111)
@@ -2298,18 +2287,10 @@ struct usart {
 
 
 
-#define USART_SR_TXE_BIT 7
-#define USART_SR_TXE_TRANSMITTED (1 << USART_SR_TXE_BIT)
+#define USART_SR_TC_BIT 6
+#define USART_SR_TC_COMPLETED (1 << USART_SR_TC_BIT)
 
 
-#define USART_SR_RXNE_BIT 5
-#define USART_SR_RXNE_READY (1 <<USART_SR_RXNE_BIT)
-
-
-
-#define USART_CR1_OVER8_BIT 15
-#define USART_CR1_OVER8_8 (1 << USART_CR1_OVER8_BIT)
-
 
 #define USART_CR1_UE_BIT 13
 #define USART_CR1_UE_ENABLE (1 << USART_CR1_UE_BIT)
@@ -2332,7 +2313,8 @@ struct usart {
 void usart2_init(void);
 void usart2_start(void);
 
-void usart2_write_byte(char byte);
+void usart2_write_byte(uint8_t byte);
+void usart2_write(char *buf);
 # 10 "src/main.c" 2
 
 #define exit 42
@@ -2346,6 +2328,9 @@ static void system_clock_init(void) {
   ((struct pwr *) (0x40007000U))->CR |= ((0b11) << 14);
 
 
+  ((struct rcc *) (0x40023800U))->CR &= ~(1 << 0);
+
+
   ((struct rcc *) (0x40023800U))->CR |= (1 << 16);
 
 
@@ -2360,7 +2345,7 @@ static void system_clock_init(void) {
   ((struct rcc *) (0x40023800U))->PLLCFGR |= (1 << 22);
 
 
-  ((struct rcc *) (0x40023800U))->PLLCFGR |= ((25 & (0b111111)) << 0) | ((196 & (0b111111111)) << 6) | ((2 & (0b11)) << 16) | ((4 & (0b1111)) << 24);
+  ((struct rcc *) (0x40023800U))->PLLCFGR |= ((25 & (0b111111)) << 0) | ((192 & (0b111111111)) << 6) | ((2 & (0b11)) << 16) | ((4 & (0b1111)) << 24);
 
 
   ((struct rcc *) (0x40023800U))->CFGR &= ~((0b1111) << 4);
@@ -2379,26 +2364,23 @@ static void system_clock_init(void) {
 
 
 
-  while (!(((struct rcc *) (0x40023800U))->CR & (1 << 17)));
+  while (!(((struct rcc *) (0x40023800U))->CR & (1 << 25)));
 
 
   ((struct flash *) (0x40023C00U))->ACR |= (1 <<10);
   ((struct flash *) (0x40023C00U))->ACR |= (1 <<9);
 
 
-  ((struct flash *) (0x40023C00U))->ACR &= ~((0b1111) << 0);
-  ((struct rcc *) (0x40023800U))->CFGR |= ((0x0111) << 0);
 
 
-  ((struct rcc *) (0x40023800U))->CFGR &= ~((0b11) << 0);
-  ((struct rcc *) (0x40023800U))->CFGR |= ((0b10) << 0);
+
+
+
+  ((struct rcc *) (0x40023800U))->CFGR |= (((0b10) & (0b11)) << 0);
 
 
 
   while (((((struct rcc *) (0x40023800U))->CFGR >> 2) & (0b11)) != (0b10));
-
-
-  ((struct rcc *) (0x40023800U))->CR &= ~(1 << 0);
 }
 
 int main(void) {
@@ -2428,7 +2410,7 @@ int main(void) {
   led_on = !led_on;
   gpio_write(led, led_on);
 
-  usart2_write_byte('a');
+  usart2_write("hello, world!\n");
 
   counter = ((struct timer *) (0x40000800U))->CNT;
  }

build/startup.S

@@ -2923,6 +2923,8 @@ interrupt_vector_table:
 	.ascii	"INOR__ >= ((maj) << 16) + (min))\000"
 .LASF171:
 	.ascii	"__DBL_MAX__ ((double)1.7976931348623157e+308L)\000"
+.LASF602:
+	.ascii	"UINTMAX_C(x) __UINTMAX_C(x)\000"
 .LASF253:
 	.ascii	"__USFRACT_MIN__ 0.0UHR\000"
 .LASF578:
@@ -3020,8 +3022,8 @@ interrupt_vector_table:
 	.ascii	"__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__\000"
 .LASF200:
 	.ascii	"__FLT32_MIN_10_EXP__ (-37)\000"
-.LASF176:
-	.ascii	"__DBL_HAS_DENORM__ 1\000"
+.LASF492:
+	.ascii	"__int20\000"
 .LASF267:
 	.ascii	"__LFRACT_IBIT__ 0\000"
 .LASF497:
@@ -3106,8 +3108,8 @@ interrupt_vector_table:
 	.ascii	"__ARM_NEON\000"
 .LASF401:
 	.ascii	"__ARM_FEATURE_CMSE\000"
-.LASF625:
-	.ascii	"/home/alex/code/own/c-compile-experiments\000"
+.LASF68:
+	.ascii	"__UINTPTR_TYPE__ unsigned int\000"
 .LASF229:
 	.ascii	"__FLT64_IS_IEC_60559__ 2\000"
 .LASF209:
@@ -3473,8 +3475,6 @@ interrupt_vector_table:
 	.ascii	"UINT16_C(x) __UINT16_C(x)\000"
 .LASF344:
 	.ascii	"__UTQ_FBIT__ 128\000"
-.LASF499:
-	.ascii	"__int20 +2\000"
 .LASF610:
 	.ascii	"long long int\000"
 .LASF24:
@@ -3539,8 +3539,8 @@ interrupt_vector_table:
 	.ascii	"__STDC__ 1\000"
 .LASF17:
 	.ascii	"__SIZEOF_LONG__ 4\000"
-.LASF492:
-	.ascii	"__int20\000"
+.LASF499:
+	.ascii	"__int20 +2\000"
 .LASF168:
 	.ascii	"__DBL_MAX_EXP__ 1024\000"
 .LASF585:
@@ -3567,6 +3567,8 @@ interrupt_vector_table:
 	.ascii	"__SCHAR_WIDTH__ 8\000"
 .LASF298:
 	.ascii	"__ACCUM_MIN__ (-0X1P15K-0X1P15K)\000"
+.LASF40:
+	.ascii	"__CHAR16_TYPE__ short unsigned int\000"
 .LASF21:
 	.ascii	"__SIZEOF_DOUBLE__ 8\000"
 .LASF7:
@@ -3801,8 +3803,8 @@ interrupt_vector_table:
 	.ascii	"SIZE_MAX (__SIZE_MAX__)\000"
 .LASF54:
 	.ascii	"__INT_LEAST64_TYPE__ long long int\000"
-.LASF602:
-	.ascii	"UINTMAX_C(x) __UINTMAX_C(x)\000"
+.LASF128:
+	.ascii	"__INT_FAST16_MAX__ 0x7fffffff\000"
 .LASF49:
 	.ascii	"__UINT32_TYPE__ long unsigned int\000"
 .LASF183:
@@ -3879,8 +3881,8 @@ interrupt_vector_table:
 	.ascii	"INT64_MAX (__INT64_MAX__)\000"
 .LASF518:
 	.ascii	"_INT8_T_DECLARED \000"
-.LASF40:
-	.ascii	"__CHAR16_TYPE__ short unsigned int\000"
+.LASF625:
+	.ascii	"/home/alex/code/own/stm32-falling-sand\000"
 .LASF370:
 	.ascii	"__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1\000"
 .LASF151:
@@ -4044,8 +4046,8 @@ interrupt_vector_table:
 	.ascii	"__FLT32X_MAX_10_EXP__ 308\000"
 .LASF140:
 	.ascii	"__UINTPTR_MAX__ 0xffffffffU\000"
-.LASF128:
-	.ascii	"__INT_FAST16_MAX__ 0x7fffffff\000"
+.LASF176:
+	.ascii	"__DBL_HAS_DENORM__ 1\000"
 .LASF32:
 	.ascii	"__GNUC_EXECUTION_CHARSET_NAME \"UTF-8\"\000"
 .LASF475:
@@ -4072,8 +4074,6 @@ interrupt_vector_table:
 	.ascii	"long +4\000"
 .LASF534:
 	.ascii	"__int_least8_t_defined 1\000"
-.LASF68:
-	.ascii	"__UINTPTR_TYPE__ unsigned int\000"
 .LASF92:
 	.ascii	"__UINTMAX_MAX__ 0xffffffffffffffffULL\000"
 .LASF42:

build/startup.i

@@ -1,5 +1,5 @@
 # 0 "src/startup.c"
-# 1 "/home/alex/code/own/c-compile-experiments//"
+# 1 "/home/alex/code/own/stm32-falling-sand//"
 # 0 "<built-in>"
 #define __STDC__ 1
 # 0 "<built-in>"

build/timer.i

@@ -1,5 +1,5 @@
 # 0 "src/timer.c"
-# 1 "/home/alex/code/own/c-compile-experiments//"
+# 1 "/home/alex/code/own/stm32-falling-sand//"
 # 0 "<built-in>"
 #define __STDC__ 1
 # 0 "<built-in>"
@@ -2055,6 +2055,19 @@ struct rcc {
 #define RCC_CFGR_PPRE_DIV_2 (0b100)
 
 
+#define RCC_CFGR_MCO1_HSE (0b10)
+#define RCC_CFGR_MCO1_PLL (0b11)
+
+#define RCC_CFGR_MCO1_BIT 21
+#define RCC_CFGR_MCO1_MASK (0b11)
+
+#define RCC_CFGR_MCO1PRE_DIV4 (0b110)
+#define RCC_CFGR_MCO1PRE_DIV2 (0b100)
+
+#define RCC_CFGR_MCO1PRE_BIT 24
+#define RCC_CFGR_MCO1PRE_MASK (0b111)
+
+
 #define RCC_CFGR_PPRE2_BIT 13
 #define RCC_CFGR_PPRE2_MASK (0b111)
 
@@ -2082,11 +2095,6 @@ struct rcc {
 #define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT)
 
 
-
-#define RCC_AHB1ENR_GPIOAEN_BIT 0
-#define RCC_AHB1ENR_GPIOAEN_ENABLE (1 << RCC_AHB1ENR_GPIOAEN_BIT)
-
-
 #define RCC_APB1ENR_PWREN_BIT 28
 #define RCC_APB1ENR_PWREN_CLOCK_ENABLE (1 << RCC_APB1ENR_PWREN_BIT)
 
@@ -2145,7 +2153,7 @@ void tim4_init(void) {
 
 
 
-  ((struct timer *) (0x40000800U))->PSC = (uint16_t) 48000 - 1;
+  ((struct timer *) (0x40000800U))->PSC = (uint16_t) 96000 - 1;
 
 
   ((struct timer *) (0x40000800U))->ARR = (uint16_t) 0xFFFF;

build/usart.i

@@ -1,5 +1,5 @@
 # 0 "src/usart.c"
-# 1 "/home/alex/code/own/c-compile-experiments//"
+# 1 "/home/alex/code/own/stm32-falling-sand//"
 # 0 "<built-in>"
 #define __STDC__ 1
 # 0 "<built-in>"
@@ -2055,6 +2055,19 @@ struct rcc {
 #define RCC_CFGR_PPRE_DIV_2 (0b100)
 
 
+#define RCC_CFGR_MCO1_HSE (0b10)
+#define RCC_CFGR_MCO1_PLL (0b11)
+
+#define RCC_CFGR_MCO1_BIT 21
+#define RCC_CFGR_MCO1_MASK (0b11)
+
+#define RCC_CFGR_MCO1PRE_DIV4 (0b110)
+#define RCC_CFGR_MCO1PRE_DIV2 (0b100)
+
+#define RCC_CFGR_MCO1PRE_BIT 24
+#define RCC_CFGR_MCO1PRE_MASK (0b111)
+
+
 #define RCC_CFGR_PPRE2_BIT 13
 #define RCC_CFGR_PPRE2_MASK (0b111)
 
@@ -2082,11 +2095,6 @@ struct rcc {
 #define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT)
 
 
-
-#define RCC_AHB1ENR_GPIOAEN_BIT 0
-#define RCC_AHB1ENR_GPIOAEN_ENABLE (1 << RCC_AHB1ENR_GPIOAEN_BIT)
-
-
 #define RCC_APB1ENR_PWREN_BIT 28
 #define RCC_APB1ENR_PWREN_CLOCK_ENABLE (1 << RCC_APB1ENR_PWREN_BIT)
 
@@ -2128,39 +2136,19 @@ struct gpio {
   volatile uint32_t AFRH;
 };
 
-#define GPIOA_BASE_ADDR (0x40020000U)
-#define GPIOA ((struct gpio *) GPIOA_BASE_ADDR)
-
-
-#define GPIO_MODER_MODER3_BIT 7
-#define GPIO_MODER_MODER3_MASK (0b11)
-#define GPIO_MODER_MODER3_AF (0b10)
-
-#define GPIO_MODER_MODER2_BIT 4
-#define GPIO_MODER_MODER2_MASK (0b11)
-#define GPIO_MODER_MODER2_AF (0b10)
-
-
-#define GPIO_AFRL_AFRL3_BIT 12
-#define GPIO_AFRL_AFRL3_MASK (0b1111)
-#define GPIO_AFRL_AFRL3_USART2_RX (0b0111)
-
-#define GPIO_AFRL_AFRL2_BIT 8
-#define GPIO_AFRL_AFRL2_MASK (0b1111)
-#define GPIO_AFRL_AFRL2_USART2_TX (0b0111)
-
-
-
-
 
+#define GPIO_AF_MCO_1 (0b0000)
+#define GPIO_AF_USART2_RX (0b0111)
+#define GPIO_AF_USART2_TX (0b0111)
 
 #define GPIO_BASE_ADDR (0x40020000U)
 #define GPIO_PORT_OFFSET (0x400U)
 #define GPIO(port) ((struct gpio*)(uintptr_t)(GPIO_BASE_ADDR + (GPIO_PORT_OFFSET * port)))
 
-#define BIT(x) (1 << x)
 
-#define PIN(port,num) ((((port) - 'A') << 8) | num)
+#define PORT(port) (((port) - 'A') << 8)
+
+#define PIN(port,num) (PORT(port) | num)
 
 #define PINNUM(pin) (pin & 0b1111)
 
@@ -2174,10 +2162,11 @@ typedef enum {
 } GPIO_MODE;
 
 void gpio_set_mode(uint16_t pin, GPIO_MODE mode);
+void gpio_set_af(uint16_t pin, uint8_t af);
 void gpio_write(uint16_t pin, 
-# 66 "src/gpio.h" 3 4
+# 47 "src/gpio.h" 3 4
                              _Bool 
-# 66 "src/gpio.h"
+# 47 "src/gpio.h"
                                   val);
 # 3 "src/usart.c" 2
 # 1 "src/usart.h" 1
@@ -2201,18 +2190,10 @@ struct usart {
 
 
 
-#define USART_SR_TXE_BIT 7
-#define USART_SR_TXE_TRANSMITTED (1 << USART_SR_TXE_BIT)
+#define USART_SR_TC_BIT 6
+#define USART_SR_TC_COMPLETED (1 << USART_SR_TC_BIT)
 
 
-#define USART_SR_RXNE_BIT 5
-#define USART_SR_RXNE_READY (1 <<USART_SR_RXNE_BIT)
-
-
-
-#define USART_CR1_OVER8_BIT 15
-#define USART_CR1_OVER8_8 (1 << USART_CR1_OVER8_BIT)
-
 
 #define USART_CR1_UE_BIT 13
 #define USART_CR1_UE_ENABLE (1 << USART_CR1_UE_BIT)
@@ -2235,39 +2216,34 @@ struct usart {
 void usart2_init(void);
 void usart2_start(void);
 
-void usart2_write_byte(char byte);
+void usart2_write_byte(uint8_t byte);
+void usart2_write(char *buf);
 # 4 "src/usart.c" 2
 
 void usart2_init(void) {
 
-  ((struct rcc *) (0x40023800U))->AHB1ENR |= (1 << 0);
+  ((struct rcc *) (0x40023800U))->AHB1ENR |= (1 << ((('A') - 'A') << 8));
 
 
-  ((struct gpio *) (0x40020000U))->MODER &= ~((0b11) << 4);
-  ((struct gpio *) (0x40020000U))->MODER |= ((0b10) << 4);
-  ((struct gpio *) (0x40020000U))->MODER &= ~((0b11) << 7);
-  ((struct gpio *) (0x40020000U))->MODER |= ((0b10) << 7);
+  uint16_t txPin = (((('A') - 'A') << 8) | 2);
+  gpio_set_mode(txPin, GPIO_MODE_AF);
+  gpio_set_af(txPin, (0b0111));
 
-
-  ((struct gpio *) (0x40020000U))->AFRL &= ~((0b1111) << 8);
-  ((struct gpio *) (0x40020000U))->AFRL |= ((0b0111) << 8);
-  ((struct gpio *) (0x40020000U))->AFRL &= ~((0b1111) << 12);
-  ((struct gpio *) (0x40020000U))->AFRL |= ((0b0111) << 12);
-
-
-  ((struct rcc *) (0x40023800U))->AHB1ENR |= (1 << 17);
+  uint16_t rxPin = (((('A') - 'A') << 8) | 3);
+  gpio_set_mode(rxPin, GPIO_MODE_AF);
+  gpio_set_af(rxPin, (0b0111));
+# 29 "src/usart.c"
+  ((struct rcc *) (0x40023800U))->APB1ENR |= (1 << 17);
 
 
   ((struct usart *) (0x40004400U))->CR1 = 0;
   ((struct usart *) (0x40004400U))->CR2 = 0;
   ((struct usart *) (0x40004400U))->CR3 = 0;
-# 49 "src/usart.c"
-  ((struct usart *) (0x40004400U))->CR1 |= (1 << 15);
-
+# 52 "src/usart.c"
   ((struct usart *) (0x40004400U))->BRR &= ~((0b111111111111) << 4);
-  ((struct usart *) (0x40004400U))->BRR |= (0x34 << 4);
+  ((struct usart *) (0x40004400U))->BRR |= (0x1A << 4);
   ((struct usart *) (0x40004400U))->BRR &= ~((0b111) << 0);
-  ((struct usart *) (0x40004400U))->BRR |= (0x0 << 0);
+  ((struct usart *) (0x40004400U))->BRR |= (0x0 << 4);
 
 
   ((struct usart *) (0x40004400U))->CR1 |= (1 << 3);
@@ -2278,10 +2254,13 @@ void usart2_start(void) {
   ((struct usart *) (0x40004400U))->CR1 |= (1 << 13);
 }
 
-void usart2_write_byte(char c) {
-
+void usart2_write_byte(uint8_t c) {
   ((struct usart *) (0x40004400U))->DR = c;
 
 
-  while ((((struct usart *) (0x40004400U))->SR & (1 << 7)) == 0);
+  while (!(((struct usart *) (0x40004400U))->SR & (1 << 6)));
+}
+
+void usart2_write(char *buf) {
+  while (*buf) usart2_write_byte(*buf++);
 }

flake.nix

@@ -5,36 +5,38 @@
     nixpkgs.url = "github:nixos/nixpkgs/nixos-unstable";
   };
 
-  outputs = { nixpkgs, ... }:
+  outputs =
+    { nixpkgs, ... }:
     let
       systems = [ "x86_64-linux" ];
     in
-      {
-        config = {
-          nixpkgs.config.allowUnfree = true;
-        };
-
-        devShells = nixpkgs.lib.genAttrs systems (system:
-          let
-            # pkgs = nixpkgs.legacyPackages.${system};
-            pkgs = import nixpkgs {
-              inherit system;
-              config.allowUnfree = true;
-            };
-          in
-            {
-              default = pkgs.mkShell {
-                packages = [
-                  pkgs.gnumake
-                  pkgs.gcc-arm-embedded
-                  pkgs.stlink
-                  pkgs.gdb
-                  pkgs.openocd
-                  pkgs.stm32cubemx
-                  pkgs.gdbgui
-                ];
-              };
-            }
-        );
+    {
+      config = {
+        nixpkgs.config.allowUnfree = true;
       };
+
+      devShells = nixpkgs.lib.genAttrs systems (
+        system:
+        let
+          # pkgs = nixpkgs.legacyPackages.${system};
+          pkgs = import nixpkgs {
+            inherit system;
+            config.allowUnfree = true;
+          };
+        in
+        {
+          default = pkgs.mkShell {
+            packages = [
+              pkgs.gnumake
+              pkgs.gcc-arm-embedded
+              pkgs.stlink
+              pkgs.gdb
+              pkgs.openocd
+              pkgs.gdbgui
+              pkgs.stm32cubemx
+            ];
+          };
+        }
+      );
+    };
 }

src/flash.h

@@ -25,7 +25,7 @@ struct flash {
 #define FLASH_ACR_ICEN_ENABLE (1 <<FLASH_ACR_ICEN_BIT)
 
 // Latency
-#define FLASH_ACR_LATENCY_3_WAIT_STATES (0x0111)
+#define FLASH_ACR_LATENCY_3_WAIT_STATES (0b0011)
 
 #define FLASH_ACR_LATENCY_BIT 0 // Bits [3:0]
 #define FLASH_ACR_LATENCY_MASK (0b1111)

src/gpio.c

@@ -6,8 +6,20 @@
 void gpio_set_mode(uint16_t pin, GPIO_MODE mode) {
   struct gpio *gpio = GPIO(PINPORT(pin));     // GPIO port address
   int pn = PINNUM(pin);                       // Pin number
-  gpio->MODER &= ~(0x0011 << (pn * 2));       // Clear existing setting. Each pin uses 2 bits
-  gpio->MODER |= (mode & 0b011) << (pn * 2);  // Set new mode. Each pin uses 2 bits
+  gpio->MODER &= ~(0b11 << (pn * 2));         // Clear existing setting. Each pin uses 2 bits
+  gpio->MODER |= (mode & 0b11) << (pn * 2);   // Set new mode. Each pin uses 2 bits
+}
+
+void gpio_set_af(uint16_t pin, uint8_t af) {
+  struct gpio *gpio = GPIO(PINPORT(pin));
+  int pn = PINNUM(pin);
+  if (pn < 8) {
+	gpio->AFRL &= ~(0b1111 << (pn * 4)); // Each pin uses 4 bits
+	gpio->AFRL |= (af & 0b1111) << (pn * 4);
+  } else {
+	gpio->AFRH &= ~(0b1111 << (pn * 4)); // Each pin uses 4 bits
+	gpio->AFRH |= (af & 0b1111) << (pn * 4);
+  }
 }
 
 void gpio_write(uint16_t pin, bool val) {

src/gpio.h

@@ -17,39 +17,19 @@ struct gpio {
   volatile uint32_t AFRH;     // Alternative function high register
 };
 
-#define GPIOA_BASE_ADDR (0x40020000U)
-#define GPIOA ((struct gpio *) GPIOA_BASE_ADDR)
-
-// MODER register
-#define GPIO_MODER_MODER3_BIT 7 // Bits [7:6]
-#define GPIO_MODER_MODER3_MASK (0b11)
-#define GPIO_MODER_MODER3_AF (0b10)
-
-#define GPIO_MODER_MODER2_BIT 4 // Bits [5:4]
-#define GPIO_MODER_MODER2_MASK (0b11)
-#define GPIO_MODER_MODER2_AF (0b10)
-
-// AFRL register
-#define GPIO_AFRL_AFRL3_BIT 12 // Bits [15:12]
-#define GPIO_AFRL_AFRL3_MASK (0b1111)
-#define GPIO_AFRL_AFRL3_USART2_RX (0b0111) // Alternative function 7
-
-#define GPIO_AFRL_AFRL2_BIT 8 // Bits [11:8]
-#define GPIO_AFRL_AFRL2_MASK (0b1111)
-#define GPIO_AFRL_AFRL2_USART2_TX (0b0111) // Alternative function 7
-
-
-
-
-
+// AFRH, AFRL registers
+#define GPIO_AF_MCO_1 (0b0000)     // Alternative function 0 (AF0)
+#define GPIO_AF_USART2_RX (0b0111) // Alternative function 7 (AF7)
+#define GPIO_AF_USART2_TX (0b0111) // Alternative function 7 (AF7)
 
 #define GPIO_BASE_ADDR (0x40020000U)
 #define GPIO_PORT_OFFSET (0x400U)
 #define GPIO(port) ((struct gpio*)(uintptr_t)(GPIO_BASE_ADDR + (GPIO_PORT_OFFSET * port)))
 
-#define BIT(x) (1 << x)
+// Create a 8bit number from a port
+#define PORT(port) (((port) - 'A') << 8)
 // Create a 16bit number from a port and pin
-#define PIN(port, num) ((((port) - 'A') << 8) | num)
+#define PIN(port, num) (PORT(port) | num)
 // get the lower byte from a PIN
 #define PINNUM(pin) (pin & 0b1111)
 // get the upper byte from a PIN
@@ -63,6 +43,7 @@ typedef enum {
 } GPIO_MODE;
 
 void gpio_set_mode(uint16_t pin, GPIO_MODE mode);
+void gpio_set_af(uint16_t pin, uint8_t af);
 void gpio_write(uint16_t pin, bool val);
 
 #endif

src/main.c

@@ -18,6 +18,9 @@ static void system_clock_init(void) {
   PWR->CR &= ~(PWR_CR_VOS_MASK << PWR_CR_VOS_BIT);
   PWR->CR |= (PWR_SCALE3 << PWR_CR_VOS_BIT);
 
+  // Turn off HSI (which is on by default)
+  RCC->CR &= ~RCC_CR_HSION_ON;
+
   // Turn on HSE
   RCC->CR |= RCC_CR_HSEON_ON;
 
@@ -33,7 +36,7 @@ static void system_clock_init(void) {
   RCC->PLLCFGR |= RCC_PLLCFGR_PLLSRC_HSE;
 
   // Settings to achieve system clock of 96Mhz
-  RCC->PLLCFGR |= RCC_PLLCFGR_PLLM(25) | RCC_PLLCFGR_PLLN(196) | RCC_PLLCFGR_PLLP(2) | RCC_PLLCFGR_PLLQ(4);
+  RCC->PLLCFGR |= RCC_PLLCFGR_PLLM(25) | RCC_PLLCFGR_PLLN(192) | RCC_PLLCFGR_PLLP(2) | RCC_PLLCFGR_PLLQ(4);
 
   // Set AHB prescalar to /1
   RCC->CFGR &= ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_BIT);
@@ -52,26 +55,23 @@ static void system_clock_init(void) {
 
   // Wait indefinitely for PLL to be ready
   // TODO indicate error/timeout somehow?
-  while (!(RCC->CR & RCC_CR_HSERDY_READY));
+  while (!(RCC->CR & RCC_CR_PLLRDY_LOCKED));
 
   // Enable caching of instructions and data
   FLASH->ACR |= FLASH_ACR_DCEN_ENABLE;
   FLASH->ACR |= FLASH_ACR_ICEN_ENABLE;
 
+  // TODO breaks with these flash settings on; turning off for now
   // Set latency to be 3 wait states (TODO: understand why exactly 3)
-  FLASH->ACR &= ~(FLASH_ACR_LATENCY_MASK << FLASH_ACR_LATENCY_BIT);
-  RCC->CFGR |= (FLASH_ACR_LATENCY_3_WAIT_STATES << FLASH_ACR_LATENCY_BIT);
+  /* FLASH->ACR &= ~(FLASH_ACR_LATENCY_MASK << FLASH_ACR_LATENCY_BIT); */
+  /* RCC->CFGR |= (FLASH_ACR_LATENCY_3_WAIT_STATES << FLASH_ACR_LATENCY_BIT); */
 
   // Use PLL as system clock
-  RCC->CFGR &= ~(RCC_CFGR_SW_MASK << RCC_CFGR_SW_BIT);
-  RCC->CFGR |= (RCC_CFGR_SW_PLL << RCC_CFGR_SW_BIT);
+  RCC->CFGR |= RCC_CFGR_SW(RCC_CFGR_SW_PLL);
 
   // Wait indefinitely for PLL clock to be selected
   // TODO indicate error/timeout somehow?
   while (((RCC->CFGR >> RCC_CFGR_SWS_BIT) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL);
-
-  // Turn off HSI (which is on by default)
-  RCC->CR &= ~RCC_CR_HSION_ON;
 }
 
 int main(void) {
@@ -83,7 +83,7 @@ int main(void) {
   (void) usart2_start();
 
   uint16_t led = PIN('C', 13);           // Blue LED
-  RCC->AHB1ENR |= BIT(PINPORT(led));     // Enable GPIO clock for LED
+  RCC->AHB1ENR |= (1 << PINPORT(led));   // Enable GPIO clock for LED
   gpio_set_mode(led, GPIO_MODE_OUTPUT);  // Set blue LED to output mode
 
   uint16_t counter = TIM4->CNT;
@@ -93,7 +93,7 @@ int main(void) {
 	 led_on = !led_on;
 	 gpio_write(led, led_on);
 
-	 usart2_write_byte('a');
+	 usart2_write("hello, world!\n");
 
 	 counter = TIM4->CNT;
 	}

src/rcc.h

@@ -87,6 +87,19 @@ struct rcc {
 #define RCC_CFGR_PPRE_DIV_NONE	0
 #define RCC_CFGR_PPRE_DIV_2	(0b100)
 
+// Microcontroller clock output 1
+#define RCC_CFGR_MCO1_HSE (0b10)
+#define RCC_CFGR_MCO1_PLL (0b11)
+
+#define RCC_CFGR_MCO1_BIT 21 // Bits [22:21]
+#define RCC_CFGR_MCO1_MASK (0b11)
+
+#define RCC_CFGR_MCO1PRE_DIV4 (0b110)
+#define RCC_CFGR_MCO1PRE_DIV2 (0b100)
+
+#define RCC_CFGR_MCO1PRE_BIT 24 // Bits [26:24]
+#define RCC_CFGR_MCO1PRE_MASK (0b111)
+
 // APB2
 #define RCC_CFGR_PPRE2_BIT 13 // Bits [15:13]
 #define RCC_CFGR_PPRE2_MASK (0b111)
@@ -114,11 +127,6 @@ struct rcc {
 #define RCC_CFGR_SW_MASK (0b11)
 #define RCC_CFGR_SW(clock) ((clock & RCC_CFGR_SW_MASK) << RCC_CFGR_SW_BIT)
 
-// AHB1ENR Register
-// GPIOA AHB1ENR
-#define RCC_AHB1ENR_GPIOAEN_BIT 0
-#define RCC_AHB1ENR_GPIOAEN_ENABLE (1 << RCC_AHB1ENR_GPIOAEN_BIT)
-
 // APB1ENR Register
 #define RCC_APB1ENR_PWREN_BIT 28
 #define RCC_APB1ENR_PWREN_CLOCK_ENABLE (1 << RCC_APB1ENR_PWREN_BIT)

src/timer.c

@@ -10,8 +10,8 @@ void tim4_init(void) {
   TIM4->CR2 = 0x0000;
 
   // Set prescaler
-  // f_clk = 48MHz -> /48000 = 1KHz counting frequency = 1ms
-  TIM4->PSC = (uint16_t) 48000 - 1;
+  // f_clk = 96MHz -> 96E6/96E3 = 1E3 = 1KHz counting frequency = 1ms
+  TIM4->PSC = (uint16_t) 96000 - 1;
 
   // Set ARR to maximum value to get 1ms between updates
   TIM4->ARR = (uint16_t) 0xFFFF;

src/usart.c

@@ -3,23 +3,30 @@
 #include "usart.h"
 
 void usart2_init(void) {
-  // Enable clock for GPIOA
-  RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN_ENABLE;
+  // Enable clock for GPIOA as USART2 is on PORT A pins
+  RCC->AHB1ENR |= (1 << PORT('A'));
 
   // Configure PA2 and PA3 (USART2 pins) to use alternative functions
-  GPIOA->MODER &= ~(GPIO_MODER_MODER2_MASK << GPIO_MODER_MODER2_BIT);
-  GPIOA->MODER |= (GPIO_MODER_MODER2_AF << GPIO_MODER_MODER2_BIT);
-  GPIOA->MODER &= ~(GPIO_MODER_MODER3_MASK << GPIO_MODER_MODER3_BIT);
-  GPIOA->MODER |= (GPIO_MODER_MODER3_AF << GPIO_MODER_MODER3_BIT);
+  uint16_t txPin = PIN('A', 2);
+  gpio_set_mode(txPin, GPIO_MODE_AF);
+  gpio_set_af(txPin, GPIO_AF_USART2_TX);
 
-  // Set pin alternative modes to use USART
-  GPIOA->AFRL &= ~(GPIO_AFRL_AFRL2_MASK << GPIO_AFRL_AFRL2_BIT);
-  GPIOA->AFRL |= (GPIO_AFRL_AFRL2_USART2_TX << GPIO_AFRL_AFRL2_BIT);
-  GPIOA->AFRL &= ~(GPIO_AFRL_AFRL3_MASK << GPIO_AFRL_AFRL3_BIT);
-  GPIOA->AFRL |= (GPIO_AFRL_AFRL3_USART2_RX << GPIO_AFRL_AFRL3_BIT);
+  uint16_t rxPin = PIN('A', 3);
+  gpio_set_mode(rxPin, GPIO_MODE_AF);
+  gpio_set_af(rxPin, GPIO_AF_USART2_RX);
+
+  // Enable MC01; for debugging
+  /* uint16_t clockOutPin = PIN('A', 8); */
+  /* gpio_set_mode(clockOutPin, GPIO_MODE_AF); */
+  /* gpio_set_af(clockOutPin, GPIO_AF_MCO_1); */
+  /* RCC->CFGR &= ~(RCC_CFGR_MCO1_MASK << RCC_CFGR_MCO1_BIT); */
+  /* RCC->CFGR |= (RCC_CFGR_MCO1_HSE << RCC_CFGR_MCO1_BIT); */
+  /* RCC->CFGR |= (RCC_CFGR_MCO1_PLL << RCC_CFGR_MCO1_BIT); */
+  /* RCC->CFGR &= ~(RCC_CFGR_MCO1PRE_MASK << RCC_CFGR_MCO1PRE_BIT); */
+  /* RCC->CFGR |= (RCC_CFGR_MCO1PRE_DIV4 << RCC_CFGR_MCO1PRE_BIT); */
 
   // Enable USART
-  RCC->AHB1ENR |= RCC_APB1ENR_USART2EN_ENABLE;
+  RCC->APB1ENR |= RCC_APB1ENR_USART2EN_ENABLE;
 
   // Clear control registers
   USART2->CR1 = 0;
@@ -27,31 +34,25 @@ void usart2_init(void) {
   USART2->CR3 = 0;
 
   // Calculate Baud rate:
-  // baud = f_clock / (8 * (2 - OVER8) * USARTDIV); =>
-  // (8 * (2 - OVER8) * USARTDIV) = f_clock / baud; =>
-  // USARTDIV = (f_clock / (baud * (8 * (2 - OVER8))); =>
+  // baud = f_clck / (8 * (2 - OVER8) * USARTDIV) =>
+  // (8 * (2 - OVER8) * USARTDIV) = f_clock / baud =>
+  // baud * (8 * (2 - OVER8) * USARTDIV) = f_clock =>
+  // USARTDIV = (f_clock / (baud * (8 * (2 - OVER8)))
 
-  // Target Baud rate = 115200, f_clock = 48MHz
+  // Target Baud rate = 115200, f_clock = 48MHz, OVER8 = 0
+  // USARTDIV = 48E6 / (115200 * 8 * 2) = 26.0416666
+  // mantissa = 26 = 0x1A
+  // fraction = 0.041666 * 16 = 0.666656 ~= 1
 
-  // With OVER8 = 1 (oversampling by 8)
-  // USARTDIV = (48E6 / (115200 * (8 * (2 - 1))) = 52.083
-  // mantissa = 52
-  // fraction = 0.083 * 8 = 0.664 ~= 1
-
-  // rounding fraction up: USARTDIV = 53
-  // baud = 48E6 / (8 * (52 + 1)) = 113207.54716981133
-  // error of 0.1% (115200 / 113207.54716981133)
-
-  // rounding fraction down: USARTDIV = 52
-  // baud = 48E6 / (8 * 52) = 115384.61538461539
-  // error of 0.001% (115384.61538461539 / 115200)
-
-  USART2->CR1 |= USART_CR1_OVER8_8;
+  // baud = 48E6 / (8 * 2 * 26) = 115384.61538461539
+  // error of 0.16% (115384.61538461539 / 115200 ) = 1.001602564102564
+  //
+  // skipping fractional part as error rate is good.
 
   USART2->BRR &= ~(USART_BRR_MANTISSA_MASK << USART_BRR_MANTISSA_BIT);
-  USART2->BRR |= (0x34 << USART_BRR_MANTISSA_BIT);
+  USART2->BRR |= (0x1A << USART_BRR_MANTISSA_BIT);
   USART2->BRR &= ~(USART_BRR_FRACTION_MASK << USART_BRR_FRACTION_BIT);
-  USART2->BRR |= (0x0 << USART_BRR_FRACTION_BIT);
+  USART2->BRR |= (0x0 << USART_BRR_MANTISSA_BIT);
 
   // Enable transmitter and receiver
   USART2->CR1 |= USART_CR1_TE_ENABLE;
@@ -62,10 +63,13 @@ void usart2_start(void) {
   USART2->CR1 |= USART_CR1_UE_ENABLE;
 }
 
-void usart2_write_byte(char c) {
-  // Send data
+void usart2_write_byte(uint8_t c) {
   USART2->DR = c;
 
   // Wait indefinitely for transmission to be ready for data
-  while ((USART2->SR & USART_SR_TXE_TRANSMITTED) == 0);
+  while (!(USART2->SR & USART_SR_TC_COMPLETED));
+}
+
+void usart2_write(char *buf) {
+  while (*buf) usart2_write_byte(*buf++);
 }

src/usart.h

@@ -10,26 +10,18 @@ struct usart {
   volatile uint32_t CR1;  // Control register 1
   volatile uint32_t CR2;  // Control register 2
   volatile uint32_t CR3;  // Control register 3
-  volatile uint32_t GTPR; // Guard time and prescaler registe
+  volatile uint32_t GTPR; // Guard time and prescaler register
 };
 
 #define USART2_BASE_ADDR (0x40004400U)
 #define USART2 ((struct usart *) USART2_BASE_ADDR)
 
 // SR Register
-// Transmission data register empty
-#define USART_SR_TXE_BIT 7
-#define USART_SR_TXE_TRANSMITTED (1 << USART_SR_TXE_BIT)
-
-// Read data register not empty
-#define USART_SR_RXNE_BIT 5
-#define USART_SR_RXNE_READY (1 <<USART_SR_RXNE_BIT)
+// Transmission complete
+#define USART_SR_TC_BIT 6
+#define USART_SR_TC_COMPLETED (1 << USART_SR_TC_BIT)
 
 // CR Register
-// Oversampling mode
-#define USART_CR1_OVER8_BIT 15
-#define USART_CR1_OVER8_8 (1 << USART_CR1_OVER8_BIT)
-
 // USART enable
 #define USART_CR1_UE_BIT 13
 #define USART_CR1_UE_ENABLE (1 << USART_CR1_UE_BIT)
@@ -44,14 +36,15 @@ struct usart {
 
 // BRR Register
 #define USART_BRR_MANTISSA_BIT 4 // Bits [15:4]
-#define USART_BRR_MANTISSA_MASK (0b111111111111) // Bits [15:4]
+#define USART_BRR_MANTISSA_MASK (0b111111111111)
 
 #define USART_BRR_FRACTION_BIT 0 // Bits [3:0]
-#define USART_BRR_FRACTION_MASK (0b111) // Bits [3:0]
+#define USART_BRR_FRACTION_MASK (0b111)
 
 void usart2_init(void);
 void usart2_start(void);
 
-void usart2_write_byte(char byte);
+void usart2_write_byte(uint8_t byte);
+void usart2_write(char *buf);
 
 #endif

todo.txt

@@ -1,2 +0,0 @@
-- implement UART
-- implement tim4 interrupt